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    Coded signal synchronizing device
    1.
    发明授权
    Coded signal synchronizing device 失效
    编码信号同步装置

    公开(公告)号：US3883687A

    公开(公告)日：1975-05-13

    申请号：US40083173

    申请日：1973-09-26

    Applicant: CIT ALCATEL

    Inventor： STENSTROM CLAUDE

    IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/493 ,  H03K5/00 ,  H03K13/00

    CPC classification number: H04L25/493 ,  H04L7/033

    Abstract: The invention concerns a device for the synchronizing, at the receiving end, of a sequence of bits used for identifying the instant at which a telegraphic transition appears in intervals of time having a uniform length, that synchronizing being based on a counting of intervals not comprising a transition.

    Abstract translation: 本发明涉及一种用于在接收端同步用于识别在具有均匀长度的时间间隔内出现电报转换的时刻的比特序列的装置，该同步基于不包括的间隔的计数 过渡。

    3.
    发明专利
    未知

    公开(公告)号：DE2233597A1

    公开(公告)日：1973-01-18

    申请号：DE2233597

    申请日：1972-07-07

    Applicant: CIT ALCATEL

    Inventor： STENSTROM CLAUDE ,  LAMBOURG MICHEL ,  DUPREZ ROBERT

    IPC: H04J3/07 ,  H04L1/10

    Abstract: 1394561 Digital transmission; error correction COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT - ALCATEL 5 July 1972 [8 July 1971] 31537/72 Heading H4P Superfluous bits in a data bit train, called padding bits, are identified by further bits called padding indicators, and if the binary valves of the latter depart from a predetermined sequence, an error is implied which the system corrects by inverting the next padding indicator. A data bit train (lower line Fig. 1a, 1b 1c) is sampled at a higher frequency, upper line, so that a data bit is sometimes sampled twice (a, e). These are the padding bits, and are moved to the third bit position of each triplet of bits. The received train includes as every fourth bit (not seen in Fig. 1) the padding indicator bit. If this is 1, the preceding bit is a padding bit; if it is 0 the preceding bit is not a padding bit; it is data. These padding indicators occur with the pattern 01011, provided there is no transmission error and the frequencies of sample and data trains are within certain limits. Errors produce 3 1's or 2 0's in a row. A combination of two bi-stables (12, 13, Fig. 4, not shown) and logic NAND gates respond to the received train 5, out of which the padding indicators 1B are clocked at 11 by clock HB, to generate four possible patterns with the binary values of A B #A #B. Two 0's in the padding indicator sequence produce a transition of A=0, B=1 to A=0, B=0 which makes the circuit change the second 0 to a 1 in the corrected padding indicator signal IB 1 ; and three 1's produce a transition of A=1, B=1 to A=0, B = 0 which makes the circuit change the third 1 to a 0 in IB 1 . Apparent errors following and possibly arising from a correction are allowed to persist for a period of four received bits, and are only corrected then if they have not disappeared.

    DISPOSITIF NUMERIQUE DE GENERATION D'UNE ONDE MODULEE EN PHASE PAR UN SIGNAL DE DONNEES ET FILTREE
    4.
    发明专利
    DISPOSITIF NUMERIQUE DE GENERATION D'UNE ONDE MODULEE EN PHASE PAR UN SIGNAL DE DONNEES ET FILTREE 未知

    公开(公告)号：CA1059221A

    公开(公告)日：1979-07-24

    申请号：CA260078

    申请日：1976-08-27

    Applicant: CIT ALCATEL

    Inventor： STENSTROM CLAUDE ,  SAINT-SUPERY CHRISTIAN

    IPC: H03K5/04 ,  G02F1/1347 ,  H04L27/20 ,  H03H7/28 ,  H04B1/00 ,  H03K5/156

    Abstract: DESCRIPTIF Dispositif numérique de génération d'une onde modulée en phase par un signal de données et filtrée, dans lequel on engendre ladite onde sous forme d'une suite de valeurs numériques délivrées à une cadence dite de calcul, à partir de valeurs em-maganisées dans une mémoire dont la lecture est commandée par un organe de sélection recevant des l'invention, sur la phase de modulation et la phase d'une onde porteu-se. Selon l'invention, les informations sur la phase de modulation sont appliquées à l'organe de sélection à travers une ligne à retard formée de r cellules en série introduisant chacune un retard égal à une période de calcul, l'organe de sélection détermine à chaque période r informations significatives respectivement, des sommes des r valeurs retardées de la phase de modulation et de la valeur à cette période de la phase de la porteuse, et la mémoire est agencée pour délivrer, en réponse à ces r informations, r valeurs sinusoïdales correspondant auxdites sommes, multi-pliées respectivement par r coefficients prédéterminés. Un accumulateur additionne sur chaque période les valeurs issues de la mémoire en vue de former la suite devaleurs numériques définissant l'onde modulée filtrée.

    5.
    发明专利
    未知

    公开(公告)号：DK137156B

    公开(公告)日：1978-01-23

    申请号：DK524373

    申请日：1973-09-25

    Applicant: CIT ALCATEL

    Inventor： STENSTROM CLAUDE

    IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/493

    Abstract: The invention concerns a device for the synchronizing, at the receiving end, of a sequence of bits used for identifying the instant at which a telegraphic transition appears in intervals of time having a uniform length, that synchronizing being based on a counting of intervals not comprising a transition.

    7.
    发明专利
    未知

    公开(公告)号：DE2347942A1

    公开(公告)日：1974-04-11

    申请号：DE2347942

    申请日：1973-09-24

    Applicant: CIT ALCATEL

    Inventor： STENSTROM CLAUDE

    IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/493 ,  H04L5/22

    Abstract: The invention concerns a device for the synchronizing, at the receiving end, of a sequence of bits used for identifying the instant at which a telegraphic transition appears in intervals of time having a uniform length, that synchronizing being based on a counting of intervals not comprising a transition.

    8.
    发明专利
    未知

    公开(公告)号：DE2638314A1

    公开(公告)日：1977-03-10

    申请号：DE2638314

    申请日：1976-08-25

    Applicant: CIT ALCATEL

    Inventor： STENSTROM CLAUDE ,  SAINT-SUPERY CHRISTIAN

    IPC: H03K5/04 ,  G02F1/1347 ,  H04L27/20

    Abstract: A digital device has an input for receiving successive samples of input data in digital form representative of phase values zeta . A sequence of the most recent input samples is stored in an input memory. A carrier phase source provides a signal representative of the phase theta of a carrier wave. A function memory stores values of a function ki x sin ( zeta n-i+ theta n) and is addressed by first selection means which select a group corresponding to a coefficient ki and second selection means which select a member of the group corresponding to the value of ( zeta + theta ). During a calculation period the sum of all values of the function is calculated for i varying between l and a predetermined number r. Each such sum forms a sample of the output wave which is converted to analogue form and filtered to remove unwanted sampling components.

    Digital demodulator for phase modulated or FM signal - has AD converter giving quadrature outputs and digital discriminator
    10.
    发明专利
    Digital demodulator for phase modulated or FM signal - has AD converter giving quadrature outputs and digital discriminator 未知

    公开(公告)号：FR2283593A1

    公开(公告)日：1976-03-26

    申请号：FR7426597

    申请日：1974-07-31

    Applicant: CIT ALCATEL

    Inventor： AMEAU ALBERT ,  STENSTROM CLAUDE ,  MINARD FRANCIS

    IPC: H03K9/06

    Abstract: The digital demodulator is for transmissions modulated in phase or frequency by a data source. The design is intended to simplify the complex filter system normally associated with demultiplexing transmissions carried on post office telephone lines. An analogue to digital converter (3) is followed by a discriminator circuit (T) feeding an output demultiplexing stage, the three major stages being preceeded by an input level regulator and a band pass filter with a cut-off at 4KHz. The discriminator has three basic units, a computing circuit providing a discrimination signal for each route, an equalising band pass filter and a sampling type unit reproducing the telegraphy signals.

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