Bit transfer unit for digital transmission system - wih memory and write and read control circuits

    公开(公告)号:FR2304146A1

    公开(公告)日:1976-10-08

    申请号:FR7507646

    申请日:1975-03-12

    Applicant: CIT ALCATEL

    Abstract: The bit transfer unit, forming part of a digital transmission system, is used to transfer a group of bits from a first bit train to a second synchronous bit train. The group of bits are supplied to a memory (5) via a write control circuit (11) and output from the memory (5) via a read control circuit. The write control circuit (11) is associated with an adjustable register (10, 13), receiving information from the first train, and logic means (14, 17, 18), such that the recording of the information in the memory is displayed by the register for a fixed interval, to avoid recording of information simultaneous with a memory read-out operation.

    3.
    发明专利
    未知

    公开(公告)号:DE2646216A1

    公开(公告)日:1977-04-28

    申请号:DE2646216

    申请日:1976-10-13

    Applicant: CIT ALCATEL

    Abstract: PCM telephone transmission apparatus and particularly the use of several extra binary positions in a multiplex frame. These positions are used in one or several units auxiliary to the main unit which processes PCM telephone signals. The auxiliary unit(s) include(s) a signalling time base identical to the signalling time base of the main unit. The counting signals for this auxiliary time base are at a lower rate than the counting signals of the main unit, but they are applied in such a way that a part of the auxiliary time base counts at the same rate as the corresponding part of the time base in the main unit. This structure enables an evolutive use of the extra bits without modification of the main unit.

    Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident

    公开(公告)号:FR2336009A1

    公开(公告)日:1977-07-15

    申请号:FR7539071

    申请日:1975-12-19

    Applicant: CIT ALCATEL

    Abstract: Synchronisation of digital equipment located some distance from the principal equipment is obtained by compensating for transmission time delay. Clock signals are returned by the remote equipment to block the clock counter except when there is coincidence. Clock pulses are applied through a gate (7) to a binary counter (8) for application to a bipolar pulse generator (10). These signals are gated (26) with signals from a logic gating circuit (25) for transmission to the remote equipment via a two way cable. Returned signals enter an integrity detector (17) whose output is applied to a coincidence gate (23) with sync. frame signals (2). A bistable (24) ensures that the counter is blocked when non-coincidence occurs.

    6.
    发明专利
    未知

    公开(公告)号:DE2628907A1

    公开(公告)日:1977-01-27

    申请号:DE2628907

    申请日:1976-06-28

    Applicant: CIT ALCATEL

    Abstract: A main pulse train at a main frequency and at least two derived pulse trains at submultiples of the main frequency are transmitted over a transmission path, from a transmitter to a receiver, in the form of pulses of alternating polarity. A first one of the derived pulse trains is transmitted as a single violation of bipolarity in the main pulse train while a second one of the derived pulse trains is transmitted as two successive violations of bipolarity in the main pulse train. The system is applicable to multiple synchronization (bit, frame etc . . . ) in a PCM digital transmission or switching system.

    8.
    发明专利
    未知

    公开(公告)号:FR2329108A1

    公开(公告)日:1977-05-20

    申请号:FR7532057

    申请日:1975-10-20

    Applicant: CIT ALCATEL

    Abstract: PCM telephone transmission apparatus and particularly the use of several extra binary positions in a multiplex frame. These positions are used in one or several units auxiliary to the main unit which processes PCM telephone signals. The auxiliary unit(s) include(s) a signalling time base identical to the signalling time base of the main unit. The counting signals for this auxiliary time base are at a lower rate than the counting signals of the main unit, but they are applied in such a way that a part of the auxiliary time base counts at the same rate as the corresponding part of the time base in the main unit. This structure enables an evolutive use of the extra bits without modification of the main unit.

    9.
    发明专利
    未知

    公开(公告)号:FR2316674A1

    公开(公告)日:1977-01-28

    申请号:FR7521091

    申请日:1975-07-04

    Applicant: CIT ALCATEL

    Abstract: A main pulse train at a main frequency and at least two derived pulse trains at submultiples of the main frequency are transmitted over a transmission path, from a transmitter to a receiver, in the form of pulses of alternating polarity. A first one of the derived pulse trains is transmitted as a single violation of bipolarity in the main pulse train while a second one of the derived pulse trains is transmitted as two successive violations of bipolarity in the main pulse train. The system is applicable to multiple synchronization (bit, frame etc . . . ) in a PCM digital transmission or switching system.

    Switchable gain amplifier with frequency compensation network - has individual compensation circuits which act independently on each of amplifiers pass bands for its N gains

    公开(公告)号:FR2291642A1

    公开(公告)日:1976-06-11

    申请号:FR7437417

    申请日:1974-11-13

    Applicant: CIT ALCATEL

    Abstract: The multiple gain switchable amplifier has a high impedance input, having a differential amplifier circuit and n differential input stage fed through an input stage selector. Each input stage has two outputs connected to the inputs of the amplifier circuit, in which each differential input stage has respectively applied an analogue input signal and the output signal of the amplifier circuit through a resistive network, so as to give to the amplifier a gain value among n possible values. The amplifier has also a frequency compensation circuit composed of individual compensation circuits (R1C1, R2C2) respectively mounted between the outputs of at least the input stages (6, 7), giving to the amplifier the lowet gain values. The compensation circuits are also connected to the inputs of the amplifier through means (d1 d'1, d2 d'2) controlled by the corresponding input stage, so as to independently connect them to the amplifier circuits inputs or to isolate them from these inputs.

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