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公开(公告)号：CA2119174C
公开(公告)日：1998-10-20
申请号：CA2119174
申请日：1994-03-16
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , THOME GARY W , SANTELER PAUL A , BONELLA RANDY M , COLLINS MICHAEL J
Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
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公开(公告)号：DE69427421D1
公开(公告)日：2001-07-19
申请号：DE69427421
申请日：1994-03-22
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , SANTELER PAUL A , THOME GARY W , BONELLA RANDY M , COLLINS MICHAEL J
Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
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Patent Agency Ranking
公开(公告)号：AT202227T
公开(公告)日：2001-06-15
申请号：AT94302014
申请日：1994-03-22
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , SANTELER PAUL A , THOME GARY W , BONELLA RANDY M , COLLINS MICHAEL J
Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
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公开(公告)号：JPH1145128A
公开(公告)日：1999-02-16
申请号：JP15732798
申请日：1998-06-05
Applicant: COMPAQ COMPUTER CORP
Inventor： SANTELER PAUL A , BACCHUS REZA M , SABOTTA MICHAEL L
Abstract: PROBLEM TO BE SOLVED: To permit the hot plug-in/out of two adapter cards including one for backup. SOLUTION: Two sets of plural electric contacts are provided inside two connectors 38 provided on an I/O board 26, and respective cards 30 are equipped with two sets of plural electric contacts to be respectively connected with two sets of electric contacts in the connectors when the cards are pluged into the connectors. One set of electric contacts in the connector is connected to a peripheral mutual connecting bus structure (trace 56) and the other set of electric contacts is connected to a mutual control bus link (trace 58a) and connected to a cable connector 32 by an electric bus structure 60. Peripheral elements and cards are connected to a host processor by the trace 56 and the mutual communication of cards is provided by the trace 58a. When ejecting one card, it is not necessary to disconnect the cable from the card because of electric bus structure so that this card can be ejected without disturbing the other function.
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公开(公告)号：DE69427421T2
公开(公告)日：2001-11-15
申请号：DE69427421
申请日：1994-03-22
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , SANTELER PAUL A , THOME GARY W , BONELLA RANDY M , COLLINS MICHAEL J
Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
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公开(公告)号：CA2119174A1
公开(公告)日：1994-09-23
申请号：CA2119174
申请日：1994-03-16
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , THOME GARY W , SANTELER PAUL A , BONELLA RANDY M , COLLINS MICHAEL J
Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
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公开(公告)号：CA2118662A1
公开(公告)日：1994-09-23
申请号：CA2118662
申请日：1994-03-09
Applicant: COMPAQ COMPUTER CORP
Inventor： SANTELER PAUL A , THOME GARY W
Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller utilizes different speed memory devices at each memory devices optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory system includes a single chip which provides all of the address and control signals to a memory device so that a clock cycle can be saved because of reduced skew of the signals. The signals are provided synchronously from the chip.
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