公开(公告)号：CA2121720A1

公开(公告)日：1994-04-14

申请号：CA2121720

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA L ,  WOLFORD JEFF W ,  MORIARTY MICHAEL ,  CULLEY PAUL R ,  SCHNELL ARNOLD T

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: RESERVATION OVERRIDING NORMAL PRIORITIZATION OF MICROPROCESSORS IN MULTIPROCESSING COMPUTER SYSTEMS Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：CA2057249A1

公开(公告)日：1992-06-22

申请号：CA2057249

申请日：1991-12-09

Applicant: COMPAQ COMPUTER CORP

Inventor： GOSS DOUGLAS A ,  SCHNELL ARNOLD T

IPC: G06F3/06 ,  G06F11/22 ,  G06F13/00 ,  G06F13/42

Abstract: SIGNAL CONDITIONING LOGIC An apparatus for conditioning signals output from a computer system expansion card to a computer system board to test system board bus specifications and timing limits. The apparatus comprises two signal conditioning extension cards which are used to condition signals from a slave card and a bus master card. The signal conditioning extension cards according to the present invention are interposed between the bus master or slave expansion card and the system board and selectively advance or delay the signals output from the expansion card to the system board. The slave signal conditioning card also selectively delays the read data valid window of the slave card to test the limits of the system board. The bus master signal conditioning card selectively delays the write data valid window of the bus master card to test the limits of the system board.

公开(公告)号：AU5168993A

公开(公告)日：1994-04-26

申请号：AU5168993

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA L ,  WOLFORD JEFF W ,  MORIARTY MICHAEL ,  CULLEY PAUL R ,  SCHNELL ARNOLD T

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：AT173842T

公开(公告)日：1998-12-15

申请号：AT93922810

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA L ,  WOLFORD JEFF W ,  MORIARTY MICHAEL ,  CULLEY PAUL R ,  SCHNELL ARNOLD T

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.