公开(公告)号：DE69322248T2

公开(公告)日：1999-04-22

申请号：DE69322248

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA ,  WOLFORD JEFF ,  MORIARTY MICHAEL ,  CULLEY PAUL ,  SCHNELL ARNOLD

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：CA2145316A1

公开(公告)日：1994-04-14

申请号：CA2145316

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E ,  MORIARTY MICHAEL ,  TAYLOR MARK

IPC: G06F13/36 ,  G06F13/364 ,  G06F15/16

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：CA2121720A1

公开(公告)日：1994-04-14

申请号：CA2121720

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA L ,  WOLFORD JEFF W ,  MORIARTY MICHAEL ,  CULLEY PAUL R ,  SCHNELL ARNOLD T

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: RESERVATION OVERRIDING NORMAL PRIORITIZATION OF MICROPROCESSORS IN MULTIPROCESSING COMPUTER SYSTEMS Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：DE69307717D1

公开(公告)日：1997-03-06

申请号：DE69307717

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER ,  MORIARTY MICHAEL ,  TAYLOR MARK

IPC: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：AU3313595A

公开(公告)日：1996-04-26

申请号：AU3313595

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  LARSON JOHN E ,  THOME GARY W ,  COLLINS MICHAEL J ,  MORIARTY MICHAEL

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/00 ,  G06F17/30

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：CA2160200A1

公开(公告)日：1996-04-15

申请号：CA2160200

申请日：1995-10-10

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  LARSON JOHN E ,  THOME GARY W ,  COLLINS MICHAEL J ,  MORIARTY MICHAEL

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/08

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：AU703750B2

公开(公告)日：1999-04-01

申请号：AU3313595

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  LARSON JOHN E ,  THOME GARY W ,  COLLINS MICHAEL J ,  MORIARTY MICHAEL

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/00 ,  G06F17/30

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：AU5440894A

公开(公告)日：1994-04-26

申请号：AU5440894

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E ,  MORIARTY MICHAEL ,  TAYLOR MARK

IPC: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：AU5168993A

公开(公告)日：1994-04-26

申请号：AU5168993

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA L ,  WOLFORD JEFF W ,  MORIARTY MICHAEL ,  CULLEY PAUL R ,  SCHNELL ARNOLD T

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：DE69322248D1

公开(公告)日：1999-01-07

申请号：DE69322248

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA ,  WOLFORD JEFF ,  MORIARTY MICHAEL ,  CULLEY PAUL ,  SCHNELL ARNOLD

IPC: G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.