公开(公告)号：CA2160525A1

公开(公告)日：1996-04-15

申请号：CA2160525

申请日：1995-10-13

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  STEVENS JEFFREY C ,  TUBBS MICHAEL E ,  STANCIL CHARLES J

IPC: G06F1/32 ,  G06F12/08

Abstract: A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：AU3313795A

公开(公告)日：1996-04-26

申请号：AU3313795

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  STEVENS JEFFREY C ,  TUBBS MICHAEL E ,  STANCIL CHARLES J

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/30

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：AU4221993A

公开(公告)日：1993-11-29

申请号：AU4221993

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORP

Inventor： WUNDERLICH RUSSELL J ,  TAYLOR MARK ,  STANCIL CHARLES J ,  HUNSAKER MIKAL C ,  BELMONT BRIAN V

IPC: G06F12/06 ,  G06F12/14

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided. The RAM is only programmed once, with modifications to the RAM-provided write protect status and memory location values being made based on write protect and relocation status information contained in a separate register.

公开(公告)号：AU4221893A

公开(公告)日：1993-11-29

申请号：AU4221893

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORP

Inventor： STANCIL CHARLES J

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F15/78

公开(公告)号：CA2112752A1

公开(公告)日：1993-11-11

申请号：CA2112752

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORP

Inventor： STANCIL CHARLES J

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F15/78

Abstract: SIGNAL ROUTING CIRCUIT FOR MICROPROCESSOR UPGRADE SOCKET A computer system can be upgraded from a 386 main CPU to a 486 microprocessor without exchanging the processor card or removing the 386 microprocessor. The computer includes a single empty socket which can be fitted with a 486SX, 487SX, or 486DX microprocessor. Any of these microprocessors can be plugged into the socket, which causes the cache system which includes an 82395 to enter a tri-state test mode and suspends the operation of the main CPU. To correct for the variations in the pin arrangements of each processor, various system signals are routed using switches to different pins for different microprocessors. In addition, specific system signals are rerouted among the system components using a set of six switches to provide for proper operation when the socket is empty and when it is occupied. By appropriately setting all of the switches, the correct signals are provided to each pin of the upgrade microprocessor. While the cache system remains in test mode, the main CPU remains fundamentally inactive, and the upgrade processor controls the computer system.