公开(公告)号：AU3727893A

公开(公告)日：1993-09-13

申请号：AU3727893

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  RAMSEY JENS K ,  BONELLA RANDY M ,  KELLY PHILIP C

IPC: G06F12/08 ,  G06F13/16

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

公开(公告)号：AU3313795A

公开(公告)日：1996-04-26

申请号：AU3313795

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  STEVENS JEFFREY C ,  TUBBS MICHAEL E ,  STANCIL CHARLES J

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/30

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：JPH1055334A

公开(公告)日：1998-02-24

申请号：JP16206397

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  GOODRUM ALAN L ,  CULLEY PAUL R

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To prevent a CPU from spending its time for waiting for the end of an I/O access and also to prevent other bus masters from being kept waiting for a long time by performing an arbitration among the bus devices via an arbiter and also performing the arbitration between the CPU and another bus device when the CPU has a request. SOLUTION: The PCI arbiters 116 and 124 are added to the bridge chips 26 and 48. All masters placed on a PCI bus 32 have the same priority as the chip 48 in an arbitration scheme of 2nd level that is carried out by the arbiter 124 in its normal operation. Then an arbitration protocol of 2nd level includes a delayed request given from a CPU, a request given from a master having a retry and an arbitration scheme of 1st level, i.e., a round-rofin scheme among the masters which are selected by the arbitration scheme of 2nd level.

公开(公告)号：JPH1055338A

公开(公告)日：1998-02-24

申请号：JP16207697

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  RAMSEY JENS K ,  CULLEY PAUL R ,  MILLER JOSEPH P

IPC: G06F13/36 ,  G06F1/12 ,  G06F13/40 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To properly transmit data among two devices by generating a 1st and a 2nd clocks by a 1st and a 2nd devices to give these clocks to other devices and preparing a receiving interface to the 1st device to synchronize the received data with the 1st clock. SOLUTION: Bridge chips 26 and 48 are used in a pair, and a PCI-PCI bridge is formed between a primary PCI bus 24 and a secondary PCI bus 32. A clock generator contained in the chip 26 generates the clocks based on a clock PCICLK 1 put on the bus 24, and one of these generated clocks is supplied to the clock generator of the chip 48 of the downstream side via a cable 28. The clock generator of the chip 48 generates a PCI clock in an extended box 30 with the same frequency as the bus 24. Thus, both bridges 26 and 48 operate by the same frequency.

公开(公告)号：CA2160525A1

公开(公告)日：1996-04-15

申请号：CA2160525

申请日：1995-10-13

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  STEVENS JEFFREY C ,  TUBBS MICHAEL E ,  STANCIL CHARLES J

IPC: G06F1/32 ,  G06F12/08

Abstract: A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：AU658503B2

公开(公告)日：1995-04-13

申请号：AU3727893

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  RAMSEY JENS K ,  BONELLA RANDY M ,  KELLY PHILIP C

IPC: G06F12/08 ,  G06F13/16

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

公开(公告)号：CA2108618A1

公开(公告)日：1993-08-22

申请号：CA2108618

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  RAMSEY JENS K ,  BONELLA RANDY M ,  KELLY PHILIP C

IPC: G06F12/08 ,  G06F13/16

Abstract: CACHE SNOOP REDUCTION AND LATENCY PREVENTION APPARATUS A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

公开(公告)号：EP0811924A3

公开(公告)日：1998-12-30

申请号：EP97303799

申请日：1997-06-04

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  GOODRUM ALAN L ,  CULLEY PAUL R

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/364

Abstract: Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.