公开(公告)号：DE69626485T2

公开(公告)日：2003-09-11

申请号：DE69626485

申请日：1996-12-10

Applicant: COMPAQ COMPUTER CORP

Inventor： WANNER CHRISTOPHER C ,  STEVENS JEFFREY C ,  LESTER ROBERT A ,  RILEY DWIGHT D ,  MAGUIRE DAVID J ,  EDWARDS JAMES R

IPC: G06F13/12 ,  G06F13/28

公开(公告)号：DE69626485D1

公开(公告)日：2003-04-10

申请号：DE69626485

申请日：1996-12-10

Applicant: COMPAQ COMPUTER CORP

Inventor： WANNER CHRISTOPHER C ,  STEVENS JEFFREY C ,  LESTER ROBERT A ,  RILEY DWIGHT D ,  MAGUIRE DAVID J ,  EDWARDS JAMES R

IPC: G06F13/12 ,  G06F13/28

公开(公告)号：AU703750B2

公开(公告)日：1999-04-01

申请号：AU3313595

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  LARSON JOHN E ,  THOME GARY W ,  COLLINS MICHAEL J ,  MORIARTY MICHAEL

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/00 ,  G06F17/30

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：AU3727893A

公开(公告)日：1993-09-13

申请号：AU3727893

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  RAMSEY JENS K ,  BONELLA RANDY M ,  KELLY PHILIP C

IPC: G06F12/08 ,  G06F13/16

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

公开(公告)号：AU3313595A

公开(公告)日：1996-04-26

申请号：AU3313595

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  LARSON JOHN E ,  THOME GARY W ,  COLLINS MICHAEL J ,  MORIARTY MICHAEL

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/00 ,  G06F17/30

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：CA2160200A1

公开(公告)日：1996-04-15

申请号：CA2160200

申请日：1995-10-10

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  LARSON JOHN E ,  THOME GARY W ,  COLLINS MICHAEL J ,  MORIARTY MICHAEL

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/08

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：CA2160525A1

公开(公告)日：1996-04-15

申请号：CA2160525

申请日：1995-10-13

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  STEVENS JEFFREY C ,  TUBBS MICHAEL E ,  STANCIL CHARLES J

IPC: G06F1/32 ,  G06F12/08

Abstract: A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：AU658503B2

公开(公告)日：1995-04-13

申请号：AU3727893

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  RAMSEY JENS K ,  BONELLA RANDY M ,  KELLY PHILIP C

IPC: G06F12/08 ,  G06F13/16

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

公开(公告)号：CA2108618A1

公开(公告)日：1993-08-22

申请号：CA2108618

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORP

Inventor： STEVENS JEFFREY C ,  RAMSEY JENS K ,  BONELLA RANDY M ,  KELLY PHILIP C

IPC: G06F12/08 ,  G06F13/16

Abstract: CACHE SNOOP REDUCTION AND LATENCY PREVENTION APPARATUS A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

公开(公告)号：AU3313795A

公开(公告)日：1996-04-26

申请号：AU3313795

申请日：1995-10-09

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  STEVENS JEFFREY C ,  TUBBS MICHAEL E ,  STANCIL CHARLES J

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/30

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.