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公开(公告)号：JPH10154064A
公开(公告)日：1998-06-09
申请号：JP31222197
申请日：1997-11-13
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T , LANDRY JOHN A , WATTS ROBERT F
Abstract: PROBLEM TO BE SOLVED: To simultaneously perform a full duplex speakerphone operation and audio reproduction like a game, etc., without an external Codec. SOLUTION: At the time of a speakerphone mode, a multiplexer 75 selects a speakerphone audio line 77, a signal sent from a DSP(digital signal processor) interface is supplied to the left channel of a D/A converter 63 and outputted as a left audio output via a mixer 59. When synthetic audio is desired to be reproduced even in a speakerphone mode, a multiplexer 81 selects the output of a mixer 79 a monotone digital signal which represents the sum of left and right audio channels which are synthesized is outputted as a right audio output via the right channel of the converter 63 and the mixer 59. Therefore, audio reproduction of a game, etc., is heard through the right speaker, while audio reproduction of a full duplex speakerphone operation is heard through the left speaker.
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公开(公告)号：DE69621711T2
公开(公告)日：2002-11-07
申请号：DE69621711
申请日：1996-07-30
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T
IPC: H03G3/34
Abstract: An apparatus is described for providing power management of a computer. The apparatus includes circuitry configured to assert a power down signal when a low power mode is to be entered and to de-assert the power down signal when the low power mode is to be exited. An audio amplifier has a power input and a mute input, and a switch is connected to the power input and configured to selectively supply power to the power input. A power down circuit is provided responsive to the power down signal and connected to the mute input and the switch such that when the power down signal is asserted, the power down circuit activates the mute input and subsequently closes the switch, and when the power down signal is de-asserted, the power down circuit opens the switch and subsequently deactivates the mute input.
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Patent Agency Ranking
公开(公告)号：DE69621711D1
公开(公告)日：2002-07-18
申请号：DE69621711
申请日：1996-07-30
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T
IPC: H03G3/34
Abstract: An apparatus is described for providing power management of a computer. The apparatus includes circuitry configured to assert a power down signal when a low power mode is to be entered and to de-assert the power down signal when the low power mode is to be exited. An audio amplifier has a power input and a mute input, and a switch is connected to the power input and configured to selectively supply power to the power input. A power down circuit is provided responsive to the power down signal and connected to the mute input and the switch such that when the power down signal is asserted, the power down circuit activates the mute input and subsequently closes the switch, and when the power down signal is de-asserted, the power down circuit opens the switch and subsequently deactivates the mute input.
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公开(公告)号：CA2057400A1
公开(公告)日：1992-06-29
申请号：CA2057400
申请日：1991-12-11
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T , ABDOO DAVID G
Abstract: A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e. g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input cloak signal, so that harmonic noise is reduced in the system.
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公开(公告)号：DE69736338T2
公开(公告)日：2007-07-12
申请号：DE69736338
申请日：1997-01-17
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T
Abstract: An audio power management system for a computer eliminates audible noise associated with the cycling of power to an audio amplifier for a computer. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the power supply. The apparatus mutes the amplifier for a brief period shortly after power becomes available and mutes the amplifier immediately when power is removed to eliminate transient noises. In one embodiment, the muting of the audio amplifier is accomplished by FET switches. In a second embodiment, the muting of the audio amplifier is accomplished by analog switches. Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power has been applied to the amplifier. This control is economically accomplished using a minimal number of digital outputs.
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公开(公告)号：DE69736338D1
公开(公告)日：2006-08-31
申请号：DE69736338
申请日：1997-01-17
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T
Abstract: An audio power management system for a computer eliminates audible noise associated with the cycling of power to an audio amplifier for a computer. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the power supply. The apparatus mutes the amplifier for a brief period shortly after power becomes available and mutes the amplifier immediately when power is removed to eliminate transient noises. In one embodiment, the muting of the audio amplifier is accomplished by FET switches. In a second embodiment, the muting of the audio amplifier is accomplished by analog switches. Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power has been applied to the amplifier. This control is economically accomplished using a minimal number of digital outputs.
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公开(公告)号：CA2057400C
公开(公告)日：2001-03-13
申请号：CA2057400
申请日：1991-12-11
Applicant: COMPAQ COMPUTER CORP
Inventor： TRAN THANH T , ABDOO DAVID G
Abstract: A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e. g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input cloak signal, so that harmonic noise is reduced in the system.
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