公开(公告)号：WO1994009435A1

公开(公告)日：1994-04-28

申请号：PCT/US1993009557

申请日：1993-10-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CHANDLER, Gregory, T. ,  GRIEFF, Thomas, W. ,  CALLISON, Ryan, A.

IPC: G06F13/12

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0692

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer butfer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

Abstract translation: 一种磁盘阵列控制器板，其使用作为其内部数据总线上的从机的EISA总线主机，以允许先进的驱动器阵列控制器芯片（ADAC）作为主机操作。 ADAC连接到传输缓冲RAM。 内部数据总线的协议提供了将主机存储器地址加载到总线从站中的周期，以提供传输计数信息和从属特定信息以及一系列数据传输周期。 本地处理器连接到EISA总线主控和ADAC控制操作并提供某些信息。 ADAC由称为命令描述符块（CDB）的结构控制。 每个CDB包括描述ADAC用于执行其传送操作的各种地址，控制位和功能位的信息。 本地处理器直接将形成CDB的数据写入并存入转移RAM。 ADAC获得CDB，将数据加载到寄存器中，然后根据这些寄存器中包含的信息执行操作，直到传输完成。 ADAC本身执行操作，包括自动条纹散射和收集，以从条形阵列数据开发连续的主机内存字段。 一系列CDB可以链接，以便可以开发一系列复杂的任务。 在一个变化中，开发了一串CDB来传输数据，但是一些数据被传送到比特桶，而其他数据被实际传输。

公开(公告)号：WO1994009436A1

公开(公告)日：1994-04-28

申请号：PCT/US1993009784

申请日：1993-10-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CALLISON, Ryan, A. ,  CHANDLER, Gregory, T. ,  GRIEFF, Thomas, W.

IPC: G06F13/12

CPC classification number: G06F3/0601 ,  G06F12/0866 ,  G06F13/124 ,  G06F2003/0692

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

Abstract translation: 一种磁盘阵列控制器板，其使用作为其内部数据总线上的从机的EISA总线主机，以允许先进的驱动器阵列控制器芯片（ADAC）作为主机操作。 ADAC连接到传输缓冲RAM。 内部数据总线的协议提供了将主机存储器地址加载到总线从站中的周期，以提供传输计数信息和从属特定信息以及一系列数据传输周期。 本地处理器连接到EISA总线主控和ADAC控制操作并提供某些信息。 ADAC由称为命令描述符块（CDB）的结构控制。 每个CDB包括描述ADAC用于执行其传送操作的各种地址，控制位和功能位的信息。 本地处理器直接将形成CDB的数据写入并存储到传送缓冲器RAM中。 ADAC获得CDB，将数据加载到寄存器中，然后根据这些寄存器中包含的信息执行操作，直到传输完成。 ADAC本身执行操作，包括自动条纹散射和收集，以从条形阵列数据开发连续的主机内存字段。 一系列CDB可以链接，以便可以开发一系列复杂的任务。 在一个变化中，开发了一串CDB来传输数据，但是一些数据被传送到比特桶，而其他数据被实际传输。

公开(公告)号：EP0664907A1

公开(公告)日：1995-08-02

申请号：EP93923791.0

申请日：1993-10-04

Applicant: Compaq Computer Corporation

Inventor： CHANDLER, Gregory, T. ,  GRIEFF, Thomas, W. ,  CALLISON, Ryan, A.

IPC: G06F3 ,  G06F13

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0692

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer butfer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.