公开(公告)号：DE69420565D1

公开(公告)日：1999-10-14

申请号：DE69420565

申请日：1994-10-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： CACCIOLA GIOVANNA ,  LEONARDI SALVATORE ,  MONTALBANO GIANPIERO

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/092

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

公开(公告)号：DE69420565T2

公开(公告)日：2000-03-30

申请号：DE69420565

申请日：1994-10-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： CACCIOLA GIOVANNA ,  LEONARDI SALVATORE ,  MONTALBANO GIANPIERO

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/092

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.