公开(公告)号：JPH07111329A

公开(公告)日：1995-04-25

申请号：JP30736791

申请日：1991-11-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： FUERUTSUCHIO FURIISHINA ,  NERA TABUOORO ,  MARIO RASUPARIISHI

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78

Abstract: PURPOSE: To make it possible to constantly keep intrinsic resistance distribution in thickness direction and along the surface of a semiconductor slice by a method wherein the transimplantation of platinum ions is conducted before formation of a contact point and conduction of a metallization process on the backside of a silicon slice against the semiconductor device after a heat process at high temperature. CONSTITUTION: Chemical etching is conducted on the rear surface of a substrate 1, where a total heat treatment process is conducted for the purpose of removing the oxide layer generated as a matter of cource on the rear surface of the substrate 1 where a total heat treatment process is conducted at a high temperature. Subsequently, platinum ions are transplanted. Then, an aperture at contact point reaching the lower layer of source region 4 is formed by etching a passivation oxide 7 for the purpose of providing a window 12. A part of the oxide 7 is left in the amount with which a gate electrode 5 can be insulated from a source metallized layer 9 which is vapor deposited on the whole surface of the device. Thereafter, a metallized layer 11 is vapor deposited on the rear of the substrate 1 for drain metallization. Accordingly, a flat and controlled intrinsic resistance distribution can be formed in thickness direction of a silicon slice.