公开(公告)号：JPH0613556A

公开(公告)日：1994-01-21

申请号：JP30482391

申请日：1991-11-20

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： SANTO PUTSUZOORO ,  RAFUAERE ZANBURAANO ,  MARIO PAPAARO

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

Abstract: PURPOSE: To enable to manufacture a structure simply and economically by laminating the bipolar power transistor and the low-voltage bipolar transistor which has an emitter-switching circuit constitution or a semi-bridge circuit constitution. CONSTITUTION: A second-conductive type first region 3, which constitutes the base of a bipolar power transistor Tp provided in first-conductive type semiconductor substrates 1 and 2, is provided. Furthermore, the emitter of the power transistor Tp provided in the first region 3 is constituted, and a first-conductive type embedded region 4 constituting the collector of a low-voltage bipolar transistor Ts is provided at the same time. In addition, a second-conductive type epitaxial layer 5, which is grown on the entire surface of the chip, is provided. A second-conductive type region 8, which is extended until the contact with the region 3 in this epitaxial layer 5 and formed, so as to surround the collector region 5 of the low voltage transistor Ts , is also provided. Thus, the power transistor Tp and the low-voltage transistor Ts can be laminated on the same semiconductor chip.

公开(公告)号：JPH07183302A

公开(公告)日：1995-07-21

申请号：JP22960994

申请日：1994-09-26

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERE ZANBURAANO

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78

Abstract: PURPOSE: To prevent damage, e.g. penetration of a metal layer, during a bonding process by setting the thickness of a metallizing region at least two times as thick as a metal interconnection line. CONSTITUTION: A first metal layer 12 is etched selectively and coated with a layer of passivation material, e.g. phosphorus silicate glass, after an interconnection line pattern is defined between cells 1. The passivation layer 13 is then removed selectively at the parts corresponding to bonding areas 14, 15 and a second metal layer 16 is connected with the first metal layer 12. In this regard, the second metal layer 16 has same composition as the first metal layer 12 and formed thicker than the first metal layer 12. Since a cell 1 is not subjected to damage during a process for connecting wires 17, 18, a dedicated area for bonding is not required and the surface area of a chip can be decreased furthermore.

公开(公告)号：JPH06302826A

公开(公告)日：1994-10-28

申请号：JP32552092

申请日：1992-12-04

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERE ZANBURAANO

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE: To reduce the possibility of the short-circuit between a gate and source regions of an IGFET. CONSTITUTION: An n-type Si layer 2 is epitaxially grown in a single crystal substrate, the surface is oxidized to form a field oxide film 4, ions are implanted in the Si layer and diffused to form a bulk region and source region and a gate polycrystalline Si layer 5 is laminated and selectively etched to form a gate electrode.