公开(公告)号：JPH09232567A

公开(公告)日：1997-09-05

申请号：JP29406296

申请日：1996-11-06

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： FURISHINA FUERUTSUCHIO ,  FUEERA JIYUSETSUPE ,  RINAUDO SARUBUATOORE

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce the capacitance between a gate and a drain by providing a basic unit having a first specific resistance value and formed in a semiconductor material layer, and a low-dope region having a second specific resistance value greater than the first specific resistance value. SOLUTION: A low-dope semiconductor layer 2 is formed on a high-dope semiconductor substrate 1. The epitaxial layer 2 forms a common drain layer, and a basic function unit has a main frame region 3 of P-conduction type. A high-dope source region 4 of N-conduction type is provided inside the main frame region 3. The top surface of the epitaxial layer 2 is covered with an insulating gate layer, and a hole is opened therein on the main frame region 3. The insulating gate layer is covered with an insulating material layer 7, and a contact window is opened therein on the main frame region 3. A region 20 having the same conduction type as and higher specific resistance than the epitaxial layer 2 is provided on the lower side of the main frame region 3. Thus, a MOS gate power device having low output resistance and low capacitance may be provided.