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    2.
    发明专利
    未知

    公开(公告)号：DE69500311T2

    公开(公告)日：1997-10-02

    申请号：DE69500311

    申请日：1995-06-05

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLA VALTER ,  PELLEGRINO PAOLO

    IPC: H01S5/042 ,  H01S5/062 ,  H01S3/096 ,  H05B33/08

    Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.

    3.
    发明专利
    未知

    公开(公告)号：DE687046T1

    公开(公告)日：1996-11-28

    申请号：DE95108625

    申请日：1995-06-05

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLA VALTER ,  PELLEGRINO PAOLO

    IPC: H01S5/042 ,  H01S5/062 ,  H01S3/096 ,  H05B33/08

    Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.

    5.
    发明专利
    未知

    公开(公告)号：IT1268070B1

    公开(公告)日：1997-02-20

    申请号：ITTO940462

    申请日：1994-06-06

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLA VALTER ,  PELLEGRINO PAOLO

    IPC: H01S5/042 ,  H01S5/062

    Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.

    6.
    发明专利
    未知

    公开(公告)号：ITTO930955D0

    公开(公告)日：1993-12-16

    申请号：ITTO930955

    申请日：1993-12-16

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLA VALTER ,  FINOTELLO ANDREA ,  GALGANI DANILO ,  GANDINI MARCO

    IPC: H03L7/087 ,  H04L7/00 ,  H04L7/033 ,  H04L27/227

    Abstract: CMOS technology high speed digital signal transceiver, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

    8.
    发明专利
    未知

    公开(公告)号：IT1272078B

    公开(公告)日：1997-06-11

    申请号：ITTO930955

    申请日：1993-12-16

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLA VALTER ,  FINOTELLO ANDREA ,  GALGANI DANILO ,  GANDINI MARCO

    IPC: H03L7/087 ,  H04L7/00 ,  H04L7/033 ,  H04L27/227 ,  H04L

    Abstract: CMOS technology high speed digital signal transceiver, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

    10.
    发明专利
    未知

    公开(公告)号：ITTO930955A1

    公开(公告)日：1995-06-16

    申请号：ITTO930955

    申请日：1993-12-16

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLA VALTER ,  FINOTELLO ANDREA ,  GALGANI DANILO ,  GANDINI MARCO

    IPC: H03L7/087 ,  H04L7/00 ,  H04L7/033 ,  H04L27/227

    Abstract: CMOS technology high speed digital signal transceiver, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

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