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1.发明授权Switching system for PCM communication with alternate voice and data transmission 失效用于PCM通信的交换系统，具有备用语音和数据传输
公开(公告)号：US3922497A
公开(公告)日：1975-11-25
申请号：US45354674
申请日：1974-03-21
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： ARTOM AURO , DEMICHELIS CARLO
Abstract: To enable selective voice communication and data transmission between calling and called subscribers of a PCM telephone network served by a central office, the latter includes a processor which intervenes during data transmission but is bypassed during voice communication while preserving the information required for instantaneous resumption of data transmission. The processor includes two buffer registers MCD1, MCD2 for incoming and outgoing message signals and two service registers MS1, MS2 for ancillary information, each register having a multiplicity of stages which are allocated to respective channels of a PCM frame and are scanned simultaneously with corresponding stages of the other registers. Calling and called subscribers are assigned separate line links giving access to respective channels via corresponding register stages, with transfer of message signals from a stage of register MCD1 (temporarily assigned to one subscriber) to a stage of register MCD2 (temporarily assigned to the other subscriber) under the control of a programmer during data transmission. This transfer is discontinued during voice communication while the contents of the associated stages of the service registers MS1, MS2 remain intact.
Abstract translation: 为了实现由中央局服务的PCM电话网络的呼叫和被叫用户之间的选择性语音通信和数据传输，后者包括在数据传输期间干预但在语音通信期间被旁路的处理器，同时保留瞬时恢复数据所需的信息 传输。 该处理器包括两个用于输入和输出消息信号的缓冲寄存器MCD1，MCD2和用于辅助信息的两个服务寄存器MS1，MS2，每个寄存器具有分配给PCM帧的相应通道的多个级并且与相应级同时扫描 的其他寄存器。 呼叫和被叫用户被分配单独的线路链路，通过相应的寄存器阶段访问相应的信道，并将消息信号从寄存器MCD1（临时分配给一个用户）的级传送到寄存器MCD2的级（暂时分配给另一个用户 ）在数据传输期间由程序员控制。 在语音通信期间中止该传输，而服务寄存器MS1，MS2的相关级的内容保持不变。
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公开(公告)号：DE2813016A1
公开(公告)日：1978-10-05
申请号：DE2813016
申请日：1978-03-23
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BARCAROLI VALERIO , DEMICHELIS CARLO , GIANDONATO GIUSEPPE , GIORCELLI SILVANO
Abstract: An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus-if the latter is available-whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.
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公开(公告)号：CA2000811A1
公开(公告)日：1990-04-17
申请号：CA2000811
申请日：1989-10-16
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MATTONE PAOLO , ZAPPLORTO ALESSANDRO
Abstract: A label switching and control interface for asynchronous fast packet switching consisting of a set of label switching and cell processing units controlled by a control unit; the units operate at each multiplex level in real time through using microprogrammed logic requiring control processor intervention only at connection set-up and release. The units implement low level flow control algorithms to exploit the advantages of this configuration. A label becomes indicative of a virtual circuit which is allotted only locally to a cell, thus removing the necessity for very complex labels, while the parameters which characterize the connection which uses a particular label are stored in the unit itself. Each unit switches the label characterizing the connection at the node input multiplex with the label characterizing it at the output multiplex. At the same time it associates, with each cell, the information necessary for multiplex switching which is then carried out in a self-routing network; the cells processed in this way by each unit of the set are statistically multiplexed asynchronously and sent to a connection network termination. This termination in turn serves other asynchronous multiplexes, which can operate at different frequencies. Label switching units do not have their own operating frequency, but automatically assume that of the asynchronous multiplexer to which they are connected.
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公开(公告)号：BR8303993A
公开(公告)日：1984-03-07
申请号：BR8303993
申请日：1983-07-26
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MANCINI PAOLO , MATTONE PAOLO
Abstract: A multiple communications interface between processor and digital transmission means, such as a serial 32-channel 64 Kbit/s PCM group, able to utilize the group channels as an equal number of two-way communications paths between the processor and other nodes of a data communications system. Each path can be used for the interchange of data messages according to dialogue procedures of HDLC type, such as X25, X75 and No. 7 of CCITT.
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公开(公告)号：DK329283D0
公开(公告)日：1983-07-18
申请号：DK329283
申请日：1983-07-18
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MANCINI PAOLO , MATTONE PAOLO
Abstract: A multiple communications interface between processor and digital transmission means, such as a serial 32-channel 64 Kbit/s PCM group, able to utilize the group channels as an equal number of two-way communications paths between the processor and other nodes of a data communications system. Each path can be used for the interchange of data messages according to dialogue procedures of HDLC type, such as X25, X75 and No. 7 of CCITT.
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Patent Agency Ranking
公开(公告)号：IT1155575B
公开(公告)日：1987-01-28
申请号：IT6794482
申请日：1982-07-27
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MANCINI PAOLO , MATTONE PAOLO
Abstract: A multiple communications interface between processor and digital transmission means, such as a serial 32-channel 64 Kbit/s PCM group, able to utilize the group channels as an equal number of two-way communications paths between the processor and other nodes of a data communications system. Each path can be used for the interchange of data messages according to dialogue procedures of HDLC type, such as X25, X75 and No. 7 of CCITT.
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公开(公告)号：AU550757B2
公开(公告)日：1986-04-10
申请号：AU1733083
申请日：1983-07-27
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MANCINI PAOLO , MATTONE PAOLO
Abstract: A multiple communications interface between processor and digital transmission means, such as a serial 32-channel 64 Kbit/s PCM group, able to utilize the group channels as an equal number of two-way communications paths between the processor and other nodes of a data communications system. Each path can be used for the interchange of data messages according to dialogue procedures of HDLC type, such as X25, X75 and No. 7 of CCITT.
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公开(公告)号：DK329283A
公开(公告)日：1984-01-28
申请号：DK329283
申请日：1983-07-18
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MANCINI PAOLO , MATTONE PAOLO
Abstract: A multiple communications interface between processor and digital transmission means, such as a serial 32-channel 64 Kbit/s PCM group, able to utilize the group channels as an equal number of two-way communications paths between the processor and other nodes of a data communications system. Each path can be used for the interchange of data messages according to dialogue procedures of HDLC type, such as X25, X75 and No. 7 of CCITT.
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公开(公告)号：CA1198520A
公开(公告)日：1985-12-24
申请号：CA432551
申请日：1983-07-15
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： DEMICHELIS CARLO , MANCINI PAOLO , MATTONE PAOLO
Abstract: The invention provides a multiple communications interface between processor and digital transmission means, such as a serial 32-channel 64 Kbit/s PCM group, adapted to utilize the group channels as an equal number of two-way communications paths between the processor and other nodes of a data communications system. Each path can be used for the interchange of data messages according to dialogue procedures of HDLC type/ such as X25, X75 and No. 7 of CCITT.
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公开(公告)号：IT1082756B
公开(公告)日：1985-05-21
申请号：IT6770277
申请日：1977-03-31
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BARCAROLI VALERIO , DEMICHELIS CARLO , GIANDONATO GIUSEPPE , GIORCELLI SILVANO
Abstract: An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus-if the latter is available-whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.
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