公开(公告)号：EP0768600B1

公开(公告)日：2003-05-07

申请号：EP96307281.4

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Grieff, Thomas W. ,  Galloway, William C. ,  Carlson, Jeff M.

IPC: G06F5/06

CPC classification number: G06F5/14 ,  G06F5/06 ,  G06F5/12 ,  G06F2205/123

公开(公告)号：EP0768600A1

公开(公告)日：1997-04-16

申请号：EP96307281.4

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Grieff, Thomas W. ,  Galloway, William C. ,  Carlson, Jeff M.

IPC: G06F5/06

CPC classification number: G06F5/14 ,  G06F5/06 ,  G06F5/12 ,  G06F2205/123

Abstract: A FIFO with locked exchange capability is disclosed. The FIFO has a memory for storing and retrieving data submissions, a write address generator and a read address generator for sequentially addressing the memory. A difference counter maintains the difference between the number of writes to the queue and reads from the queue. The net difference, as tracked by the counter is a measure of the FIFO utilization. To detect the queue full condition, a comparator compares the maximum FIFO stack depth against the counter output. The result of this comparison is latched and provided to a write strobe generator so that, in a subsequent write operation, if the FIFO is full, the write strobe from the producer is blocked and the data will not be written to the FIFO. Otherwise, the write strobe from the producer is passed to the memory. Additionally, a remaining space count is maintained in a status register. During operation, a bus master performing the read-modify-write cycle to the FIFO reads the status register to find the available space in the FIFO and immediately writes the data to the FIFO. If the read returns a zero, indicating that the FIFO is full, the bus master requeues the data for another read-modify-write cycle as it knows that the data has not been stored in the FIFO.

Abstract translation: 公开了具有锁定交换能力的FIFO。 FIFO具有用于存储和检索数据提交的存储器，用于顺序寻址存储器的写入地址发生器和读取地址发生器。 差异计数器维护对队列的写入次数和从队列读取的差异。 由计数器跟踪的净差是FIFO利用率的量度。 为了检测队列满状态，比较器比较最大FIFO堆栈深度与计数器输出。 该比较的结果被锁存并提供给写选通发生器，使得在随后的写操作中，如果FIFO满，则来自制造者的写选通信号被阻塞，并且数据将不被写入到FIFO。 否则，来自制造商的写选通传递到存储器。 此外，在状态寄存器中保持剩余空间计数。 在操作期间，执行FIFO读读修改周期的总线主机读取状态寄存器以找到FIFO中的可用空间，并立即将数据写入FIFO。 如果读取返回零，表明FIFO已满，则总线主机将数据重新取出用于另一个读 - 修改 - 写入周期，因为它知道数据尚未存储在FIFO中。