公开(公告)号：EP0907129A1

公开(公告)日：1999-04-07

申请号：EP98307413.9

申请日：1998-09-14

Applicant: Compaq Computer Corporation

Inventor： Sabotta, Michael L. ,  Grieff, Thomas W.

IPC: G06F13/40

CPC classification number: G06F13/4068 ,  Y10T307/675

Abstract: An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates the device from the bus. The isolation system further includes enable logic that detects cycles on the bus and provides the enable signal to the enable input ofthe isolation device during a cycle ifthe cycle is associated with the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus. Generally, the enable logic may comprise decode logic that decodes an address on the bus during the bus cycle to determine if the address corresponds to an address of the device. Decode logic is useful for decoding a memory cycle on the bus for accessing a low voltage memory device, which is otherwise isolated from the bus.

Abstract translation: 隔离系统和方法做了电连接的装置，以一个总线或访问设备相关联的循环过程中，但在其他隔离从总线设备。 隔离系统包括：在耦合到所述器件隔离设备和所述总线确实包括在使能输入angepasst接收到使能信号，其中，所述隔离装置电耦合设备向所述总线，而所述使能信号被断言，但在其他电隔离 从总线设备。 所述隔离系统进一步包括使能逻辑做在总线上检测到周期和期间周期ifthe周期与所述设备相关联提供的使能信号，以隔离国税发装置使能输入。 隔离装置可以包括总线开关，一个或多个分立的隔离装置：如双极晶体管，场效应晶体管，或用于从总线隔离的装置的任何其它合适的装置。 一般地，使能逻辑可以包括解码逻辑解码的确，如果该地址在设备的地址对应于总线周期确定性矿期间寻址总线上。 解码逻辑是用于访问低电压存储器装置解码所述总线上的存储器周期是有用的，所有这一切都被以其他方式从总线隔离。

公开(公告)号：EP0486178A1

公开(公告)日：1992-05-20

申请号：EP91309948.7

申请日：1991-10-28

Applicant: Compaq Computer Corporation

Inventor： Dao, Hung Duy ,  Grieff, Thomas W. ,  Lattin, Thomas W., Jr. ,  Thomas, Darren R. ,  Schultz, Stephen M. ,  Ewert, Richard A. ,  Flower, David L.

IPC: G11B33/14 ,  G11B33/10

CPC classification number: G11B33/10 ,  G11B33/144

Abstract: Temperature sensors (50,52) are located inside drive chambers (30,32) where disk drives (41-48) are located to signal an overheating condition. An overheating condition triggers external alarms (36) and produces an interrupt signal to the disk drive controller (150), which, in turn, alerts the operating system. If the operating system does not comprehend the problem and take the appropriate action, the controller shuts down the disk drives after a certain period of time.

Abstract translation: 温度传感器（50,52）位于磁盘驱动器（41-48）所在的驱动室（30,32）内，以表示过热状态。 过热条件触发外部报警（36），并向磁盘驱动器控制器（150）产生一个中断信号，这又提醒操作系统。 如果操作系统不了解问题并采取适当的措施，控制器会在一段时间后关闭磁盘驱动器。

公开(公告)号：EP0858036A2

公开(公告)日：1998-08-12

申请号：EP98300808.7

申请日：1998-02-04

Applicant: Compaq Computer Corporation

Inventor： Skidmore, Alan E. ,  Schultz, Stephen M. ,  Scholhamer, George J. ,  Thompson, Mark J. ,  Rushton, Tod D. ,  Freeman, Eugene E. ,  Alexander, Dennis J. ,  Callison, Ryan A. ,  Grieff, Thomas W. ,  Sabotta, Michael L. ,  Grant, David L. ,  McCarty, James F. ,  Schneider, Randy D. ,  Galloway, William C.

IPC: G06F13/42 ,  G06F3/06 ,  H04L29/06

CPC classification number: G06F11/201 ,  H04L12/433 ,  H04L67/42

Abstract: A system and/or network (50) for connecting at least one server (52) to at least one storage device (56) via a Fibre Channel (54). Such a system is capable of providing connection redundancy, high speed data rates, multiple operating systems and, hot plugging. Furthermore, the system allows for a large number of devices to be connected to the Fibre Channel. The devices, being servers, storage devices, or other system related appliances can be separated by more than 10 miles and still communicate via the Fibre Channel at high data rates.

Abstract translation: 一种用于经由光纤通道（54）将至少一个服务器（52）连接到至少一个存储设备（56）的系统和/或网络（50）。 这样的系统能够提供连接冗余，高速数据速率，多个操作系统和热插拔。 此外，系统允许大量设备连接到光纤通道。 作为服务器，存储设备或其他系统相关设备的设备可以分开超过10英里，并且仍然通过光纤通道以高数据速率进行通信。

公开(公告)号：EP0486258A1

公开(公告)日：1992-05-20

申请号：EP91310425.3

申请日：1991-11-12

Applicant: Compaq Computer Corporation

Inventor： Grieff, Thomas W.

IPC: G06F13/42

CPC classification number: G06F13/4243

Abstract: A circuit (30) is proposed for providing wait states using address bits not used in the device address decode. The various addressed memory and peripheral devices do not utilize the entire address space and so some address bits are not utilized. A number of the unused bits are decoded (40,42) to determine the number of wait states to be developed in the operation. The address decode based wait state determination is overridden (46) for RAM operations, but followed for ROM and peripheral operations.

Abstract translation: 提出了一种电路（30），用于使用设备地址解码中未使用的地址位来提供等待状态。 各种寻址的存储器和外围设备不利用整个地址空间，因此一些地址位不被利用。 多个未使用的位被解码（40,42）以确定在操作中要开发的等待状态的数量。 基于地址解码的等待状态确定被覆盖（46）用于RAM操作，但是遵循ROM和外设操作。

公开(公告)号：EP0427119A3

公开(公告)日：1993-08-04

申请号：EP90120978.3

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Grieff, Thomas W. ,  Bush, Kenneth L.

IPC: G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0601 ,  G06F11/10 ,  G06F11/1008 ,  G06F2003/0692

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.

公开(公告)号：EP0486230A1

公开(公告)日：1992-05-20

申请号：EP91310354.5

申请日：1991-11-08

Applicant: Compaq Computer Corporation

Inventor： Lattin, Thomas W., Jr. ,  Grieff, Thomas W. ,  Callison, Ryan A.

IPC: G06F15/16 ,  G06F5/06

CPC classification number: G06F13/4226 ,  G06F13/124

Abstract: A SCSI bus controller (S) has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, (36) the other port of which is connected to a bus master controller (20) linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO (42). The local microprocessor (24) does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.

Abstract translation: SCSI总线控制器（S）具有从SCSI总线到主机总线的单独的数据路径，以及用于与本地微处理器通信的单独的命令路径。 本地微处理器连接到双端口RAM（36），另一个端口连接到与主机系统相连的总线主控制器（20）。 命令和状态通过双端口RAM传递。 数据通过FIFO（42）传递。 本地微处理器（24）不能访问数据路径，而仅控制数据流的方向，序列的启动和序列的完成。

公开(公告)号：EP0427119A2

公开(公告)日：1991-05-15

申请号：EP90120978.3

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Grieff, Thomas W. ,  Bush, Kenneth L.

IPC: G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0601 ,  G06F11/10 ,  G06F11/1008 ,  G06F2003/0692

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.

Abstract translation: 磁盘阵列控制器包括本地微处理器，总线主机接口，兼容接口，缓冲存储器和磁盘接口。 控制器包括微处理器，总线主机接口，兼容接口和缓冲存储器之间的DMA控制器。 磁盘接口和缓冲存储器之间也提供DMA控制器。 这些DMA通道之一包括用于开发与磁盘阵列一起使用的奇偶校验信息的XOR引擎。 各种DMA控制器循环，以允许访问缓冲存储器和磁盘接口。

公开(公告)号：EP0768600B1

公开(公告)日：2003-05-07

申请号：EP96307281.4

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Grieff, Thomas W. ,  Galloway, William C. ,  Carlson, Jeff M.

IPC: G06F5/06

CPC classification number: G06F5/14 ,  G06F5/06 ,  G06F5/12 ,  G06F2205/123

公开(公告)号：EP0858036A3

公开(公告)日：1999-12-22

申请号：EP98300808.7

申请日：1998-02-04

Applicant: Compaq Computer Corporation

Inventor： Skidmore, Alan E. ,  Schultz, Stephen M. ,  Scholhamer, George J. ,  Thompson, Mark J. ,  Rushton, Tod D. ,  Freeman, Eugene E. ,  Alexander, Dennis J. ,  Callison, Ryan A. ,  Grieff, Thomas W. ,  Sabotta, Michael L. ,  Grant, David L. ,  McCarty, James F. ,  Schneider, Randy D. ,  Galloway, William C.

IPC: G06F13/42 ,  G06F3/06 ,  H04L29/06

CPC classification number: G06F11/201 ,  H04L12/433 ,  H04L67/42

Abstract: A system and/or network (50) for connecting at least one server (52) to at least one storage device (56) via a Fibre Channel (54). Such a system is capable of providing connection redundancy, high speed data rates, multiple operating systems and, hot plugging. Furthermore, the system allows for a large number of devices to be connected to the Fibre Channel. The devices, being servers, storage devices, or other system related appliances can be separated by more than 10 miles and still communicate via the Fibre Channel at high data rates.

公开(公告)号：EP0824239A3

公开(公告)日：1999-07-28

申请号：EP97305893.6

申请日：1997-08-04

Applicant: Compaq Computer Corporation

Inventor： Lomelino, Lawrence W. ,  Grieff, Thomas W. ,  Sabotta, Michael L.

IPC: G06F13/42

CPC classification number: G06F13/4278

Abstract: The present invention relates to a secondary channel for a point-to-point burst style bus associated with a computer system. The point-to-point bus may originate as a standardized bus from a fibre channel controller. The point-to-point bus connects to another circuit which may be a bridge circuit, a minicomputer or a peripheral device. A secondary channel is also connected to the point-to-point bus and is adapted to share the bus by receiving information having predetermined addresses. The information recieved by the secondary channel can be stored in a memory that is shared with a processor.