公开(公告)号：EP0768607A2

公开(公告)日：1997-04-16

申请号：EP96307280.6

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Chard, Gary F.

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F2211/1054

Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

Abstract translation: 用于执行硬件辅助XOR操作以产生磁盘阵列系统的奇偶校验位的电路。 该电路包括控制器，其作为PCI总线与包括写入缓存部分和XOR缓冲器部分的DRAM之间的接口。 DRAM具有最大数据存储容量，并且控制器被分配为DRAM的最大存储容量的两倍的地址空间。 地址空间分为正常地址范围和异或地址范围两部分。 对正常地址范围的写入将产生到DRAM的正常写入周期，而对XOR地址范围的写操作会向DRAM产生读 - 修改 - 写入XOR周期。 在读取 - 修改 - 写入XOR周期中，读取数据与写入数据进行异或运算。 所选数据被累积地异或以产生新的奇偶校验信息。

公开(公告)号：EP0768607B1

公开(公告)日：2003-04-02

申请号：EP96307280.6

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Chard, Gary F.

IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F11/1076 ,  G06F2211/1054

Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

公开(公告)号：EP0768607A3

公开(公告)日：2000-03-01

申请号：EP96307280.6

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Chard, Gary F.

IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F11/1076 ,  G06F2211/1054

Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller (118) that acts as an interface between a PCI bus (102) and a DRAM (116) that includes a write-posting cache portion (136) and an XOR buffer portion (134). The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.