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    Disk drive controller with a posted write cache memory
    2.
    发明公开
    Disk drive controller with a posted write cache memory 失效
    。。。。。。。。。。。。。

    公开(公告)号：EP0582370A2

    公开(公告)日：1994-02-09

    申请号：EP93304372.1

    申请日：1993-06-04

    Applicant: Compaq Computer Corporation

    Inventor： Alexander, Dennis J. ,  Callison, Ryan A. ,  Perry, Ralph S.

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0601 ,  G06F11/1012 ,  G06F11/1076 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/74 ,  G11C29/88

    Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

    Abstract translation: 磁盘阵列控制器包括本地微处理器，总线主机接口，兼容接口，缓冲存储器和磁盘接口。 控制器包括微处理器，总线主机接口，兼容接口和缓冲存储器之间的DMA控制器。 磁盘接口和缓冲存储器之间也提供DMA控制器。 这些DMA通道之一包括用于开发与磁盘阵列一起使用的奇偶校验信息的XOR引擎。 各种DMA控制器循环，以允许访问缓冲存储器和磁盘接口。 作为可选择的磁盘驱动器将已写入的存储器系统连接到磁盘接口。 贴出的写入存储器系统包括镜像，奇偶校验和电池供电的半导体存储器，以便在断电条件下保留发布的写入数据，只有非常小的数据丢失变化。

    Disk array controller for performing exclusive or operations
    3.
    发明授权
    Disk array controller for performing exclusive or operations 失效
    磁盘阵列控制器来执行异或操作

    公开(公告)号：EP0768607B1

    公开(公告)日：2003-04-02

    申请号：EP96307280.6

    申请日：1996-10-04

    Applicant: Compaq Computer Corporation

    Inventor： Callison, Ryan A. ,  Chard, Gary F.

    IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

    CPC classification number: G06F11/1076 ,  G06F2211/1054

    Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

    Disk array controller for performing exclusive or operations
    4.
    发明公开
    Disk array controller for performing exclusive or operations 失效
    磁盘阵列控制器来执行异或操作

    公开(公告)号：EP0768607A3

    公开(公告)日：2000-03-01

    申请号：EP96307280.6

    申请日：1996-10-04

    Applicant: Compaq Computer Corporation

    Inventor： Callison, Ryan A. ,  Chard, Gary F.

    IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

    CPC classification number: G06F11/1076 ,  G06F2211/1054

    Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller (118) that acts as an interface between a PCI bus (102) and a DRAM (116) that includes a write-posting cache portion (136) and an XOR buffer portion (134). The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

    Apparatus and method for combining data streams with programmable wait states
    5.
    发明公开
    Apparatus and method for combining data streams with programmable wait states 失效
    装置和方法，用于组合的数据具有可编程等待状态流

    公开(公告)号：EP0824238A2

    公开(公告)日：1998-02-18

    申请号：EP97305892.8

    申请日：1997-08-04

    Applicant: Compaq Computer Corporation

    Inventor： Lomelino, Lawrence W. ,  Callison, Ryan A.

    IPC: G06F13/36 ,  G06F13/40

    CPC classification number: G06F13/4054 ,  G06F13/36

    Abstract: A system for transferring data includes structure (i.e, hardware, software, a combination thereof) for requesting data from a second bus, which data is destined for a first bus; and structure for gaining ownership of the second bus for the purpose of transferring the data from the second bus to the first bus, which structure includes substructure for waiting a programmably variable amount of time to see if additional data is requested by the first bus, before relinquishing control of the second bus.

    Abstract translation: 一种用于传递环数据系统包括用于从第二总线，其中数据是发送给第一总线请求数据结构（即，硬件，软件，其组合）; 和结构用于将来自第二总线获得所述第二总线的所有权转移环的目的数据到第一总线，其中结构包括子结构用于等待时间的可编程地可变的量，以看看是否还有其他数据由第一总线请求，前 放弃所述第二总线的控制。

    Disk drive controller with a posted write cache memory
    7.
    发明授权
    Disk drive controller with a posted write cache memory 失效
    与Nachschreibcachespeicher一种磁盘驱动器控制器

    公开(公告)号：EP0582370B1

    公开(公告)日：1998-10-07

    申请号：EP93304372.1

    申请日：1993-06-04

    Applicant: Compaq Computer Corporation

    Inventor： Alexander, Dennis J. ,  Callison, Ryan A. ,  Perry, Ralph S.

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0601 ,  G06F11/1012 ,  G06F11/1076 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/74 ,  G11C29/88

    Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

    Apparatus and method for combining data streams with programmable wait states
    9.
    发明公开
    Apparatus and method for combining data streams with programmable wait states 失效
    装置和方法，用于组合的数据具有可编程等待状态流

    公开(公告)号：EP0824238A3

    公开(公告)日：1999-03-24

    申请号：EP97305892.8

    申请日：1997-08-04

    Applicant: Compaq Computer Corporation

    Inventor： Lomelino, Lawrence W. ,  Callison, Ryan A.

    IPC: G06F13/36 ,  G06F13/40

    CPC classification number: G06F13/4054 ,  G06F13/36

    Abstract: A system for transferring data includes structure (i.e, hardware, software, a combination thereof) for requesting data from a second bus, which data is destined for a first bus; and structure for gaining ownership of the second bus for the purpose of transferring the data from the second bus to the first bus, which structure includes substructure for waiting a programmably variable amount of time to see if additional data is requested by the first bus, before relinquishing control of the second bus.

    Disk array controller for performing exclusive or operations
    10.
    发明公开
    Disk array controller for performing exclusive or operations 失效
    Speicherplattenanordnungs-Steuervorrichtung zurDurchführungvon Exklusif-ODER-Operationen

    公开(公告)号：EP0768607A2

    公开(公告)日：1997-04-16

    申请号：EP96307280.6

    申请日：1996-10-04

    Applicant: Compaq Computer Corporation

    Inventor： Callison, Ryan A. ,  Chard, Gary F.

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F2211/1054

    Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

    Abstract translation: 用于执行硬件辅助XOR操作以产生磁盘阵列系统的奇偶校验位的电路。 该电路包括控制器，其作为PCI总线与包括写入缓存部分和XOR缓冲器部分的DRAM之间的接口。 DRAM具有最大数据存储容量，并且控制器被分配为DRAM的最大存储容量的两倍的地址空间。 地址空间分为正常地址范围和异或地址范围两部分。 对正常地址范围的写入将产生到DRAM的正常写入周期，而对XOR地址范围的写操作会向DRAM产生读 - 修改 - 写入XOR周期。 在读取 - 修改 - 写入XOR周期中，读取数据与写入数据进行异或运算。 所选数据被累积地异或以产生新的奇偶校验信息。

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