公开(公告)号：EP0919919B1

公开(公告)日：2004-06-23

申请号：EP98309634.8

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Dean, Jeffrey A. ,  Chrysos, George Z. ,  Hicks, James E. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F8/445 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

公开(公告)号：EP0919918B1

公开(公告)日：2003-11-19

申请号：EP98309631.4

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Chrysos, George Z. ,  Dean, Jeffrey A. ,  Hicks, James E. ,  Leibholz, Daniel L. ,  McLellan, Edward J. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.

公开(公告)号：EP0919924B1

公开(公告)日：2004-09-22

申请号：EP98309672.8

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Chrysos, George Z. ,  Dean, Jeffrey A. ,  Hicks, James E. ,  Leibholz, Daniel L. ,  McLellan, Edward J. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466

Abstract: An apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. When the instructions are fetched into a first stage of the pipeline, the apparatus identifies multiple selected instructions as a subset of the instructions that one executed concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.