公开(公告)号：EP0918288B1

公开(公告)日：2004-01-21

申请号：EP98309671.0

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Dean, Jeffrey A. ,  Waldspurger, Carl A. ,  Hicks, James E. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory.

公开(公告)号：EP0919919B1

公开(公告)日：2004-06-23

申请号：EP98309634.8

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Dean, Jeffrey A. ,  Chrysos, George Z. ,  Hicks, James E. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F8/445 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

公开(公告)号：EP0919920B1

公开(公告)日：2003-04-02

申请号：EP98309638.9

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Dean, Jeffrey A. ,  Hicks, James E. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/348 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: A method estimates statistics of properties of transactions processed by a memory sub-system of a computer system. The method randomly selects memory transactions processed by the memory sub-system. States of the system are recorded as samples while the selected transaction are processed by the memory sub-system. The recorded states from a subset of the selected transactions are statistically analyzed to estimate statistics ofthe memory transactions.

公开(公告)号：EP0919918B1

公开(公告)日：2003-11-19

申请号：EP98309631.4

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Chrysos, George Z. ,  Dean, Jeffrey A. ,  Hicks, James E. ,  Leibholz, Daniel L. ,  McLellan, Edward J. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.

公开(公告)号：EP0919922B1

公开(公告)日：2003-03-05

申请号：EP98309653.8

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Dean, Jeffrey A. ,  Root, Stephen C. ,  Hicks, James E. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/3447 ,  G06F11/3466 ,  G06F2201/87 ,  G06F2201/88

Abstract: Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched Into a first stage of the pipeline. A set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other. A distances between the set of selected instructions is specified, and state information of the computer system is recorded while the set of selected instructions is being processed by the pipeline. The recorded state information is communicated to software where it is statistically analyzed for a plurality of sets of selected instructions to estimate statistics of the interactions among sets of selected instructions.

公开(公告)号：EP0919924B1

公开(公告)日：2004-09-22

申请号：EP98309672.8

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Chrysos, George Z. ,  Dean, Jeffrey A. ,  Hicks, James E. ,  Leibholz, Daniel L. ,  McLellan, Edward J. ,  Waldspurger, Carl A. ,  Weihl, William E.

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466

Abstract: An apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. When the instructions are fetched into a first stage of the pipeline, the apparatus identifies multiple selected instructions as a subset of the instructions that one executed concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.

公开(公告)号：EP0919923B1

公开(公告)日：2002-07-17

申请号：EP98309657.9

申请日：1998-11-25

Applicant: Compaq Computer Corporation

Inventor： Dean, Jeffrey A. ,  Waldspurger, Carl A.

IPC: G06F11/34

CPC classification number: G06F9/4881 ,  G06F11/3452 ,  G06F11/3466 ,  G06F11/3471 ,  G06F12/08 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: A method analyses memory transaction processed by memories of a computer system. The method selects a set of addresses of the memories. State information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transactions are processed by the memories. The selecting and the recording steps are repeated until a termination condition is reached. Then, the recorded state information is statistically analysed to estimate statistics of properties of the memory interactions among contexts in the computer system.