公开(公告)号：EP0707268A2

公开(公告)日：1996-04-17

申请号：EP95307349.1

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Stevens, Jeffrey C. ,  Thome, Gary W. ,  Larson, John E. ,  Collins, Michael J. ,  Moriarty, Michael

IPC: G06F12/06

CPC classification number: G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

Abstract translation: 用于在计算机系统的存储器控​​制器提供了一系列的处理器和PCI总线与存储器系统之间的线索。存储器一致性被保持在两种不同的方式。 之前任何读取操作从PCI总线所接受，无论是发布队列必须是空的。 内容可寻址存储器（CAM）被用作PCI到存储器队列中。 当处理器执行一个读请求时，所述CAM被检查以确定矿如果在PCI到存储器队列中的未决写操作中的一个是相同的地址作为处理器的读出手术。 这样读出的不可操作执行，直到PCI到存储器队列被清除写入如果。 要解决中止多重存储器读取手术问题的，中止从PCI总线接口信号被接收，此后只要可以做提前读周期结束，即使预读循环处理不当的全面完成。 存储器控制器具有改进的基于是否周期从处理器来或从PCI总线来允许更有效的预充电。当使用PCI总线周期的预测规则。 存储器控制器为多个速度和类型的处理器和存储器设备的几个速度高度可编程。 存储器控制器包括寄存器的多元性确实指定其用来控制状态机的操作的常规的动态随机存取存储器周期的特定部分的时钟周期的数目。

公开(公告)号：EP0707268A3

公开(公告)日：1996-07-31

申请号：EP95307349.1

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Stevens, Jeffrey C. ,  Thome, Gary W. ,  Larson, John E. ,  Collins, Michael J. ,  Moriarty, Michael

IPC: G06F12/06

CPC classification number: G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.