公开(公告)号：EP0784277A1

公开(公告)日：1997-07-16

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract translation: 一个计算机系统，在总线上具有独立但兼容的DMA控制器。 用于控制至少一个DMA通道的每个DMA控制器，每个DMA控制器具有用于执行DMA操作的独立的一组寄存器和用于指示通道状态和指定的配置寄存器。 DMA主机，用于与处理器进行兼容通信，并与多个DMA控制器进行初始化和通信。

公开(公告)号：EP0707268A3

公开(公告)日：1996-07-31

申请号：EP95307349.1

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Stevens, Jeffrey C. ,  Thome, Gary W. ,  Larson, John E. ,  Collins, Michael J. ,  Moriarty, Michael

IPC: G06F12/06

CPC classification number: G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：EP0784277B1

公开(公告)日：2003-03-05

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

公开(公告)号：EP0707256A3

公开(公告)日：1996-08-07

申请号：EP95307348.3

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Ramsey, Jens K. ,  Tubbs, Michael E. ,  Stevens, Jeffrey C. ,  Stancil, Charles J.

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3215 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F9/30083 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：EP0707268A2

公开(公告)日：1996-04-17

申请号：EP95307349.1

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Stevens, Jeffrey C. ,  Thome, Gary W. ,  Larson, John E. ,  Collins, Michael J. ,  Moriarty, Michael

IPC: G06F12/06

CPC classification number: G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

Abstract translation: 用于在计算机系统的存储器控​​制器提供了一系列的处理器和PCI总线与存储器系统之间的线索。存储器一致性被保持在两种不同的方式。 之前任何读取操作从PCI总线所接受，无论是发布队列必须是空的。 内容可寻址存储器（CAM）被用作PCI到存储器队列中。 当处理器执行一个读请求时，所述CAM被检查以确定矿如果在PCI到存储器队列中的未决写操作中的一个是相同的地址作为处理器的读出手术。 这样读出的不可操作执行，直到PCI到存储器队列被清除写入如果。 要解决中止多重存储器读取手术问题的，中止从PCI总线接口信号被接收，此后只要可以做提前读周期结束，即使预读循环处理不当的全面完成。 存储器控制器具有改进的基于是否周期从处理器来或从PCI总线来允许更有效的预充电。当使用PCI总线周期的预测规则。 存储器控制器为多个速度和类型的处理器和存储器设备的几个速度高度可编程。 存储器控制器包括寄存器的多元性确实指定其用来控制状态机的操作的常规的动态随机存取存储器周期的特定部分的时钟周期的数目。

公开(公告)号：EP0707256A2

公开(公告)日：1996-04-17

申请号：EP95307348.3

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Ramsey, Jens K. ,  Tubbs, Michael E. ,  Stevens, Jeffrey C. ,  Stancil, Charles J.

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3215 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F9/30083 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

Abstract translation: 的电路被描述为放置在外部或L2高速缓存存储器进入低功耗模式，响应于由微处理器执行特殊的某些周期。 尤其特殊的周期可能是停批承认特殊周期和停止特殊循环。 微处理器执行的停止许可确认响应特殊周期的请求被计算机系统至其时钟放慢。 该请求由所述计算机系统断言如果系统已空闲了预定的时间段。 暂停周期特殊由微处理器当HALT指令被执行生成。 该停批承认并停止特殊周期中各微处理器进入低功耗状态。 由于微处理器处于低功率模式中，L2高速缓冲存储器被如此放置进入低功耗模式为节电此外。 在L2高速缓冲存储器被实现，也与同步或异步静态随机存取存储器（SRAM）。 放置一个同步SRAM进入低功耗模式，而它的片选输入被置为无效它的地址选通输入被断言。 的异步SRAM时，解除其芯片选择输入使SRAM转变到低功率模式。