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Patent Agency Ranking
公开(公告)号：EP0426413A3
公开(公告)日：1991-12-04
申请号：EP90311839.6
申请日：1990-10-29
Applicant: Compaq Computer Corporation
Inventor： Jansen, Kenneth A. , McGraw, Montgomery C. , Miller, David A. , Culley, Paul R.
IPC: G06F13/362
CPC classification number: G06F13/362
Abstract: A bus arbitration method is disclosed for multiple processors (20,21) that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme (75). When control of the bus (54) is allocated to the single processor, the multiprocesor arbitration (134) arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means (PCL1,PCL2) for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.
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2.发明公开Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效在多个处理器系统中独立复位处理器和缓存控制器的方法和装置
公开(公告)号：EP0426366A3
公开(公告)日：1992-12-30
申请号：EP90311652.3
申请日：1990-10-24
Applicant: Compaq Computer Corporation
Inventor： Miller, David A. , Jansen, Kenneth A. , Culley, Paul R. , Taylor, Mark E. , Izquierdo, Javier F.
CPC classification number: G06F12/0802 , G06F1/24 , G06F15/177
Abstract: A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
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3.发明公开Multiprocessor arbitration in single processor arbitration schemes 失效在Einzelprotessor bestimmten Arbitrierungsschemas的Multiprozessorarbitrierung。
公开(公告)号：EP0426413A2
公开(公告)日：1991-05-08
申请号：EP90311839.6
申请日：1990-10-29
Applicant: Compaq Computer Corporation
Inventor： Jansen, Kenneth A. , McGraw, Montgomery C. , Miller, David A. , Culley, Paul R.
IPC: G06F13/362
CPC classification number: G06F13/362
Abstract: A bus arbitration method is disclosed for multiple processors (20,21) that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme (75). When control of the bus (54) is allocated to the single processor, the multiprocesor arbitration (134) arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means (PCL1,PCL2) for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.
Abstract translation: 公开了一种可被并入设计成仅包括单个处理器的仲裁方案的多个处理器（20,21）的总线仲裁方法。 该方法包括将每个处理器的各个总线请求整合到提供给单处理器仲裁方案（75）的单个总线请求中。 当总线（54）的控制被分配给单个处理器时，多处理器仲裁（134）在请求总线的处理器之间进行仲裁。 所使用的总线协议包括最近最少使用的用于授予与多个处理器的总线访问相结合的方法（PCL1，PCL2），用于给予其他处理器优先级以访问总线。 该协议还包括在预设时间段内控制总线的相应处理器的中断保护。
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4.发明授权Multiprocessor arbitration in single processor arbitration schemes 失效Multiprozessorarbitrierung在单处理器特定的仲裁方案
公开(公告)号：EP0426413B1
公开(公告)日：1997-05-07
申请号：EP90311839.6
申请日：1990-10-29
Applicant: Compaq Computer Corporation
Inventor： Jansen, Kenneth A. , McGraw, Montgomery C. , Miller, David A. , Culley, Paul R.
IPC: G06F13/362
CPC classification number: G06F13/362
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5.发明公开Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效用于处理器和高速缓冲存储器控制器的方法和装置在多处理器系统中独立地复位。
公开(公告)号：EP0426366A2
公开(公告)日：1991-05-08
申请号：EP90311652.3
申请日：1990-10-24
Applicant: Compaq Computer Corporation
Inventor： Miller, David A. , Jansen, Kenneth A. , Culley, Paul R. , Taylor, Mark E. , Izquierdo, Javier F.
CPC classification number: G06F12/0802 , G06F1/24 , G06F15/177
Abstract: A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
Abstract translation: 一种用于复位独立初级和次级处理器20和120分别在程序控制下在多处理器的方法和系统，高速缓冲存储器系统。处理器20和120是而不会引起高速缓冲存储器控制器24和124以重置复位。
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