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    Controlling a power state of a computer
    1.
    发明公开
    Controlling a power state of a computer 失效
    控制计算机的电源状态

    公开(公告)号：EP0889387A3

    公开(公告)日：2000-06-14

    申请号：EP98305147.5

    申请日：1998-06-29

    Applicant: Compaq Computer Corporation

    Inventor： Taylor, Mark E. ,  Kunkel, Larry W. ,  Bayramoglu, Gokalp ,  D'Souza, Henry M. ,  Ali, Valiuddin

    IPC: G06F1/26 ,  G06F1/32 ,  G06F1/16

    CPC classification number: G06F1/26

    Abstract: Method and apparatus of controlling a power state of a computer, the computer being connected to a monitor having a power control button. The computer is connected to the monitor over a video cable, and activation of the power control button is communicated to the computer over a wire in the video cable. In response to the activation signal, a system management interrupt is generated to invoke an SMI handler to change the power state of the computer. The power states of the computer include an ON state, an intermediate power state (such as Sleep state), and a suspend state (such as Soft-Off state).

    Improved paged memory controller
    5.
    发明公开
    Improved paged memory controller 失效
    改进的PAGED MEMORY CONTROLLER

    公开(公告)号：EP0427425A3

    公开(公告)日：1992-05-27

    申请号：EP90311650.7

    申请日：1990-10-24

    Applicant: Compaq Computer Corporation

    Inventor： Mayer, David J. ,  Culley, Paul R. ,  Taylor, Mark E.

    IPC: G06F12/02 ,  G06F12/08

    CPC classification number: G06F12/0882 ,  G06F12/0215

    Abstract: A computer system has a processor (20) coupled to a cache controller (24), uses page mode memory devices (58) sand performs page hit detection (43) on the processor local bus (26). Column address and data values are latched by a memory controller (62) on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

    Controlling a power state of a computer
    6.
    发明公开
    Controlling a power state of a computer 失效
    Steuerung des Leistungszustandes eines Rechners

    公开(公告)号：EP0889387A2

    公开(公告)日：1999-01-07

    申请号：EP98305147.5

    申请日：1998-06-29

    Applicant: Compaq Computer Corporation

    Inventor： Taylor, Mark E. ,  Kunkel, Larry W. ,  Bayramoglu, Gokalp ,  D'Souza, Henry M. ,  Ali, Valiuddin

    IPC: G06F1/26

    CPC classification number: G06F1/26

    Abstract: Method and apparatus of controlling a power state of a computer, the computer being connected to a monitor having a power control button. The computer is connected to the monitor over a video cable, and activation of the power control button is communicated to the computer over a wire in the video cable. In response to the activation signal, a system management interrupt is generated to invoke an SMI handler to change the power state of the computer. The power states of the computer include an ON state, an intermediate power state (such as Sleep state), and a suspend state (such as Soft-Off state).

    Abstract translation: 控制计算机的电源状态的方法和装置，所述计算机连接到具有电源控制按钮的监视器。 计算机通过视频电缆连接到显示器，并且电源控制按钮的激活通过视频电缆中的电线传送到计算机。 响应于激活信号，产生系统管理中断以调用SMI处理程序来改变计算机的电源状态。 计算机的电源状态包括ON状态，中间功率状态（如睡眠状态）和暂停状态（如Soft-Off状态）。

    Enhanced locked bus cycle control in a cache memory computer system
    7.
    发明公开
    Enhanced locked bus cycle control in a cache memory computer system 失效
    在缓存存储器计算机系统中增强锁定总线周期控制

    公开(公告)号：EP0425843A3

    公开(公告)日：1992-07-08

    申请号：EP90119257.5

    申请日：1990-10-08

    Applicant: Compaq Computer Corporation

    Inventor： Culley, Paul R. ,  Taylor, Mark E.

    IPC: G06F13/36

    CPC classification number: G06F13/364 ,  G06F12/0888

    Abstract: An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controller 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.

    Improved paged memory controller
    8.
    发明公开
    Improved paged memory controller 失效
    Seitenspeicher-Steuerschaltung。

    公开(公告)号：EP0427425A2

    公开(公告)日：1991-05-15

    申请号：EP90311650.7

    申请日：1990-10-24

    Applicant: Compaq Computer Corporation

    Inventor： Mayer, David J. ,  Culley, Paul R. ,  Taylor, Mark E.

    IPC: G06F12/02 ,  G06F12/08

    CPC classification number: G06F12/0882 ,  G06F12/0215

    Abstract: A computer system has a processor (20) coupled to a cache controller (24), uses page mode memory devices (58) sand performs page hit detection (43) on the processor local bus (26). Column address and data values are latched by a memory controller (62) on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

    Abstract translation: 计算机系统具有耦合到高速缓存控制器（24）的处理器（20），使用页面模式存储设备（58），沙子在处理器本地总线（26）上执行页面命中检测（43）。 列地址和数据值由存储器控制器（62）锁存在存储器写入操作上，以允许早期完成循环，使得下一个周期可以部分重叠。 这允许使用经济的记忆，而且具有零等待状态页命中操作。

    Enhanced locked bus cycle control in a cache memory computer system
    9.
    发明公开
    Enhanced locked bus cycle control in a cache memory computer system 失效
    在einem Rechnersystem mit Cache-Speicher中的Buszyklusverriegelungssteuerung。

    公开(公告)号：EP0425843A2

    公开(公告)日：1991-05-08

    申请号：EP90119257.5

    申请日：1990-10-08

    Applicant: Compaq Computer Corporation

    Inventor： Culley, Paul R. ,  Taylor, Mark E.

    IPC: G06F13/36

    CPC classification number: G06F13/364 ,  G06F12/0888

    Abstract: An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controller 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.

    Abstract translation: 一种用于计算机系统的增强的处理器锁周期管理系统，包括处理器10和高速缓冲存储器控制器12，其容纳现有方法并提供增强模式，其中处理器锁定周期不被传递到控制器12，而是由控制器12控制系统总线14 通过由其他系统元件禁止对控制器12的保持请求来维护。

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