Abstract:
A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals (15a,15b) which are connected to first and second conductor planes (44,45) in the printed circuit board (B). Three vias (41,42,43) are mounted in the printed circuit board (B) in a position to be aligned with the middle of the capacitor. A first conductor pad (45) is mounted underneath one end of the capacitor and includes spaced apart extension portions (45b,45c) which electrically attach to the first (41) and third via (43). A second conductor pad (44) is mounted under the other end of the capacitor and includes a central extension portion (44b) which attaches to the second or middle via (42). In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.