公开(公告)号：EP2768276A4

公开(公告)日：2015-07-01

申请号：EP12839896

申请日：2012-08-24

Applicant: DENSO CORP

Inventor： IRIE MASASHI ,  FUKAZAWA TAKESHI ,  YAMAGUCHI HIRONAO ,  HAYASHI NAOTO

IPC: H05B3/00 ,  F02M31/125 ,  F02P19/02 ,  F23Q7/00 ,  H05B1/02

CPC classification number: H05B1/0236 ,  F02P19/021 ,  F02P19/022 ,  F02P19/023 ,  F02P19/025 ,  F02P19/027 ,  F23Q7/001 ,  H05B2203/02 ,  H05B2203/027

公开(公告)号：DE102015118459A1

公开(公告)日：2016-05-12

申请号：DE102015118459

申请日：2015-10-29

Applicant: DENSO CORP

Inventor： FUKAZAWA TAKESHI

IPC: H01L29/87 ,  H01L29/06

Abstract: Eine Diode weist einen Körper mit einer Mehrzahl von p-n-Übergängen, Anoden- und Kathodenelektroden, eine Kurzschlusselektrode, einen Schutzring und ein Isolationsfilm auf. Der Körper mit der Mehrzahl der p-n-Übergänge weist erste bis vierte Halbleiterschichten bzw. -layer auf, welche gestapelt sind, um eine Laminierungsstruktur zwischen der Anodenelektrode und der Kathodenelektrode vorzusehen. Jeder der ersten und dritten Halbleiterlayer ist ein erster leifähiger Halbleiter. Jeder der zweiten und vierten Halbleiterlayer ist ein zweiter leitfähiger Halbleiter. Die ersten und zweiten Halbleiterlayer bilden einen p-n-Übergang aus. Die zweiten und dritten Halbleiterlayer bilden einen p-n-Übergang aus. Die dritten und vierten Halbleiterlayer bilden einen p-n-Übergang aus. Die Kurzschlusselektrode sieht einen Kurzschluss zwischen dem zweiten Halbleiterlayer und dem dritten Halbleiterlayer vor. Ein Bereich mit einer hohen Konzentration ist in einem Kontaktbereich in dem zweiten Halbleiterlayer ausgebildet. Eine Oberfläche des Kontaktbereichs steht in Kontakt mit der ersten Kurzschlusselektrode.

公开(公告)号：DE102013215427A1

公开(公告)日：2014-02-06

申请号：DE102013215427

申请日：2013-08-06

Applicant: DENSO CORP

Inventor： FUKAZAWA TAKESHI

IPC: H01L29/861 ,  H01L27/06 ,  H01L29/866

Abstract: Eine Diode wird bereitgestellt, die zumindest ein Diodenelement, das eine Vielzahl von N-Typ Bereichen und eine Vielzahl von P-Typ Bereichen aufweist, wobei die N-Typ Bereiche und die P-Typ Bereiche alternierend in Serie angebracht sind, um PN-Übergänge zu bilden, und ein Isolationssubstrat enthält, das eine elektrische Isolation aufweist. Die N-Typ Bereiche und die P-Typ Bereiche sind auf dem Isolationssubstrat gebildet.

公开(公告)号：JPH11168210A

公开(公告)日：1999-06-22

申请号：JP33443697

申请日：1997-12-04

Applicant: DENSO CORP

Inventor： TSUZUKI YUKIO ,  FUKAZAWA TAKESHI

IPC: H01L21/322 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To increase the withstand voltage of a gate insulating film by suppressing the formation of an etch pit(recess) on the inner wall of a U-shaped trench. SOLUTION: In a vertical power MOSFET, a specific region on the surface of an n type epitaxial layer 2 formed on one surface of a semiconductor substrate 1 is etched so as to form a U-shaped trensch, however, when thermal diffusing step is performed before the etching step, a gettering layer 60 is formed by phosphorus deposition on the opposite side surface to the epitaxial layer 2 on the semiconductor substrate 1 before the thermal diffusing step. Thus, the contaminating impurity metallic atoms in the n type epitaxial layer 2 can be arrested by the gettering layer 60 during heat treatment. Through these procedures, the development of the crystalline defects due to the contaminating impurity metallic stoms can be suppressed, thereby enabling the etch pit caused by the crystalline defects in the etching step to be suppressed. Resultantly, the withstand voltage of a gate oxide film can be increased.

公开(公告)号：JPH09199722A

公开(公告)日：1997-07-31

申请号：JP869896

申请日：1996-01-22

Applicant: DENSO CORP

Inventor： FUKAZAWA TAKESHI ,  KONDO ICHIJI ,  OKABE NAOTO

IPC: H01L29/78 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To lighten the stepped parts on cell surfaces and to make it possible to perform wire bonding onto a source electrode properly by adjusting the thickness of a layer insulating film in a recession of a gate electrode in a groove into a specific range. SOLUTION: A layer insulating film 18 is formed so that W

公开(公告)号：JP2013239479A

公开(公告)日：2013-11-28

申请号：JP2012109745

申请日：2012-05-11

Applicant: Denso Corp ,  株式会社デンソー

Inventor： MIZUNO DAISUKE ,  FUKAZAWA TAKESHI

IPC: H01L25/07 ,  H01L21/52 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To loosen a limit of a physical constitution of a semiconductor element while securing an insulation property of the semiconductor element and a lead frame in a semiconductor device in which plural semiconductor elements are arranged on the same plane of the lead frame.SOLUTION: A semiconductor device has: a double-side electrode element electrically connected to one face of a lead frame via lead-free solder; and a control IC electrically isolated from and connected to one face of the lead frame via an insulation adhesive. The control IC comprises: a chip section; and an insulation layer having uniform thickness across an entire opposite face of the chip section opposed to the lead frame. The insulation layer is connected to one face of the lead frame via the insulation adhesive.

Abstract translation: 要解决的问题：在确保半导体元件和引线框架的绝缘性能的同时，在半导体器件中松动半导体元件的物理结构的限制，其中多个半导体元件布置在引线框架的同一平面上。 解决方案：半导体器件具有：通过无铅焊料与引线框架的一面电连接的双面电极元件; 以及通过绝缘粘合剂与引线框架的一个表面电隔离并连接到引线框架的一个面的控制IC。 控制IC包括：芯片部分; 以及在与引线框架相对的芯片部分的整个相对面上具有均匀厚度的绝缘层。 绝缘层通过绝缘粘合剂连接到引线框架的一个表面。

公开(公告)号：JP2013011181A

公开(公告)日：2013-01-17

申请号：JP2011142779

申请日：2011-06-28

Applicant: Denso Corp ,  株式会社デンソー

Inventor： ITO KENJI ,  TAKEDA SHUNICHI ,  TORIYAMA MAKOTO ,  FUKAZAWA TAKESHI

IPC: F02P3/04 ,  H01F38/12 ,  H01L27/04 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To make both compatible in achieving high pressure of secondary voltage, shortening an ignition response time and reducing cutoff noise.SOLUTION: This ignition control device includes a main IGBT 31 (a switching element for ignition) for controlling current-carrying and cutoff to a primary coil 11, and a sub-IGBT 32 (a switching element for feedback) connected between a collector Cm and a gate Gm of the main IGBT 31 and controlling whether or not to feed back by impressing voltage of the collector Cm on the gate Gm. A parasitic capacitor Cpara existing between the collector Cs (a feedback input terminal) and the gate Gs (a feedback electric continuity control terminal) of the sub-IGBT 32, is charged with cutoff noise voltage generated in the collector Cm in response to OFF operation of the main IGBT 31, the sub-IGBT 32 performs ON operation by increasing control voltage of the gate Gs by this charge, and the sub-IGBT 32 also performs OFF operation by reducing the control voltage by discharging the parasitic capacitor Cpara.

Abstract translation: 要解决的问题：使二次电压达到高压兼容，缩短点火响应时间并减少截止噪声。 解决方案：该点火控制装置包括用于控制与初级线圈11的通电和截止的主IGBT31（用于点火的开关元件）和连接在初级线圈11之间的副IGBT32（反馈用开关元件） 集电极Cm和主IGBT31的栅极Gm，并通过在栅极Gm上施加集电极Cm的电压来控制是否反馈。 存在于集电极Cs（反馈输入端子）与副IGBT32的栅极Gs（反馈电连续性控制端子）之间的寄生电容器Cpara被充电，其中响应于OFF操作在集电极Cm中产生的截止噪声电压 在主IGBT31的情况下，副IGBT32通过增加栅极Gs的控制电压来进行ON动作，副IGBT32也通过对寄生电容Cpara进行放电来降低控制电压而进行OFF动作。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2008218688A

公开(公告)日：2008-09-18

申请号：JP2007053761

申请日：2007-03-05

Applicant: Denso Corp ,  株式会社デンソー

Inventor： SHIMOIDE SACHIHIRO ,  FUKAZAWA TAKESHI

IPC: H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To mold a plurality of semiconductor chips with a resin to reduce a packaged semiconductor device in planar size; to supplying electrical current to the semiconductor chips with low resistance; and to improve heat radiation in the semiconductor chips. SOLUTION: A battery terminal 30 for electrically connecting to a source electrode 12 in each semiconductor chip 10 is composed of one plate member. The battery terminal 30 is overlapped on respective semiconductor chips 10 to be directly connected to respective source electrodes 12 through a solder 91, thereby reducing the semiconductor device in the planar size and increasing a bonding area of respective semiconductor chips 10 and the battery terminal 30. Furthermore in the battery terminal 30, a surface on the side opposite to the side that is connected to the semiconductor chip 10 is exposed out of a mold resin 70, thereby improving the heat radiation in the semiconductor chip 10. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：用树脂模制多个半导体芯片以将封装的半导体器件减小为平面尺寸; 以低电阻向半导体芯片供电; 并且改善半导体芯片中的热辐射。 解决方案：用于电连接到每个半导体芯片10中的源电极12的电池端子30由一个板构件构成。 电池端子30通过焊料91与各个源电极12直接连接在各半导体芯片10上，从而将半导体器件减小到平面尺寸，并增加各个半导体芯片10和电池端子30的接合面积。 此外，在电池端子30中，与半导体芯片10连接的一侧的相反侧的表面从模制树脂70露出，从而改善了半导体芯片10中的热辐射。版权所有（ C）2008，JPO＆INPIT

公开(公告)号：JP2005197593A

公开(公告)日：2005-07-21

申请号：JP2004004363

申请日：2004-01-09

Applicant: Denso Corp ,  株式会社デンソー

Inventor： OZOE SHOJI ,  FUKAZAWA TAKESHI ,  MIYAJIMA TAKESHI ,  OKABE YOSHIFUMI

IPC: H01L23/50

CPC classification number: H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a lead frame structured enabling checking of electronic components and connection statuses of individual leads, before they are resin-molded, facilitating replacement of the electronic components and the reconnection of the lead frames, and manufacturing it more easily. SOLUTION: The lead frame 100 comprises a plurality of leads 10 which are to be electrically connected to the outside, and a supporter 20 in the shape of a frame, wherein individual leads 10 are fixed to and supported by the supporter 20 via an electrically insulating adhesive 30. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种引线框架，其能够在树脂模制之前对电子部件和各个引线的连接状态进行检查，便于电子部件的更换和引线框的重新连接以及制造它 更容易 引线框架100包括要与外部电连接的多个引线10和框架形式的支撑件20，其中各个引线10通过支撑件20固定并由支撑件20支撑 电绝缘粘合剂30。（C）2005，JPO＆NCIPI

公开(公告)号：JP2003318129A

公开(公告)日：2003-11-07

申请号：JP2002117604

申请日：2002-04-19

Applicant: Denso Corp ,  株式会社デンソー

Inventor： OKABE YOSHIFUMI ,  KOYAMA MASAKI ,  MIYAJIMA TAKESHI ,  FUKAZAWA TAKESHI

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having the step of forming the upper side end of a contact hole of an interlayer insulating film in a protruding shape on the upper side end without necessity of ion implanting for suppressing the increase in the contact resistance after reflowing process and to provide the semiconductor device obtained by the same.
SOLUTION: The method for manufacturing the semiconductor device comprises the steps of: forming a p-type base region 5 on an n
- -type layer 2 front layer in a semiconductor substrate 3 having an n
- -type layer 2 and forming an n
+ type source region 6 on the surface layer of the p-type base region 5; then forming an interlayer insulating film 11 on the layer 2; etching to the midway of the film 11 in a contact hole forming region; and then reflowing in the state that an interlayer insulating film 11a is retained on the layer 2. Thus, the upper side end of a contact hole 15 on the film 11 becomes a protruding curve shape on the upper side end. Thereafter, the film 11 is removed, and a source electrode 16 is formed.
COPYRIGHT: (C)2004,JPO

Abstract translation: 解决的问题：提供一种制造半导体器件的方法，该半导体器件具有以下步骤：在上侧端部形成突出形状的层间绝缘膜的接触孔的上侧端，而不需要离子注入 抑制回流后的接触电阻的增加，并提供由其获得的半导体器件。 解决方案：制造半导体器件的方法包括以下步骤：在具有n个半导体衬底3的半导体衬底3中，在n - / SP>型层2前层上形成p型基极区域5 并且在p型基底区域5的表面层上形成n + 型源极区域6; 然后在层2上形成层间绝缘膜11; 在接触孔形成区域中蚀刻到膜11的中间; 然后在层2上保持层间绝缘膜11a的状态下进行回流。因此，膜11上的接触孔15的上侧端部成为上侧的突出曲线形状。 之后，除去膜11，形成源电极16。 版权所有（C）2004，JPO