公开(公告)号：EP1721865A2

公开(公告)日：2006-11-15

申请号：EP06075963.6

申请日：2006-04-28

Applicant: Delphi Technologies, Inc.

Inventor： Rich, David B. ,  Crist, Steven M.

IPC: B81B3/00

CPC classification number: B81C1/00142 ,  B81B2201/0235 ,  B81B2201/032 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/016 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

Abstract: A technique for manufacturing a piezoresistive sensing structure (170) includes a number of process steps. Initially, a piezoresistive element (108) is implanted into a first side of an assembly (102,106,104A) that includes a semiconductor material (102,104A). A passivation layer (110A) is then formed on the first side of the assembly (102,106,104A) over the element (108). The passivation layer (110A) is then removed from selected areas on the first side of the assembly (102,106,104A). A first mask is then provided on the passivation layer (110A) in a desired pattern. A beam (152), which includes the element (108), is then formed in the assembly over at least a portion of the assembly (102,106,104A) that is to provide a cavity (103). The passivation layer (110A) provides a second mask, in the formation of the beam (152), that determines a width of the formed beam (152).

Abstract translation: 制造压阻感测结构（170）的技术包括多个工艺步骤。 最初，将压阻元件（108）注入包括半导体材料（102,104A）的组件（102,106,104A）的第一侧。 然后在元件（108）上方的组件（102,106,104A）的第一侧上形成钝化层（110A）。 然后从组件（102,106,104A）的第一侧上的选定区域去除钝化层（110A）。 然后以期望的图案在钝化层（110A）上提供第一掩模。 然后，包括元件（108）的梁（152）在组件中形成在组件（102,106,104A）的至少一部分上，以提供空腔（103）。 钝化层（110A）在确定所形成的光束（152）的宽度的波束（152）的形成中提供第二掩模。

公开(公告)号：EP1721865B1

公开(公告)日：2012-12-26

申请号：EP06075963.6

申请日：2006-04-28

Applicant: Delphi Technologies, Inc.

Inventor： Rich, David B. ,  Crist, Steven M.

IPC: B81C1/00 ,  G01P15/12

CPC classification number: B81C1/00142 ,  B81B2201/0235 ,  B81B2201/032 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/016 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

公开(公告)号：EP1721865A3

公开(公告)日：2011-09-28

申请号：EP06075963.6

申请日：2006-04-28

Applicant: Delphi Technologies, Inc.

Inventor： Rich, David B. ,  Crist, Steven M.

IPC: B81C1/00 ,  G01P15/12

CPC classification number: B81C1/00142 ,  B81B2201/0235 ,  B81B2201/032 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/016 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/0828

Abstract: A technique for manufacturing a piezoresistive sensing structure (170) includes a number of process steps. Initially, a piezoresistive element (108) is implanted into a first side of an assembly (102,106,104A) that includes a semiconductor material (102,104A). A passivation layer (110A) is then formed on the first side of the assembly (102,106,104A) over the element (108). The passivation layer (110A) is then removed from selected areas on the first side of the assembly (102,106,104A). A first mask is then provided on the passivation layer (110A) in a desired pattern. A beam (152), which includes the element (108), is then formed in the assembly over at least a portion of the assembly (102,106,104A) that is to provide a cavity (103). The passivation layer (110A) provides a second mask, in the formation of the beam (152), that determines a width of the formed beam (152).