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    Riser pipe assembly for marine applications
    3.
    发明授权
    Riser pipe assembly for marine applications 失效
    用于海洋应用的立管管组件

    公开(公告)号：US5377763A

    公开(公告)日：1995-01-03

    申请号：US199960

    申请日：1994-02-22

    Applicant: Robert G. Pearce ,  Donald D. Baldwin

    Inventor： Robert G. Pearce ,  Donald D. Baldwin

    IPC: E21B17/01 ,  E21B17/08 ,  E21B19/02

    CPC classification number: E21B17/01 ,  E21B17/085

    Abstract: A riser pipe assembly is provided for interconnecting a subsea wellhead on an ocean floor with an above-surface platform. The assembly includes at least one cable extending generally between the wellhead and the platform to provide vertical support for the assembly. A plurality of support plates are fixed to the cable at predetermined spaced locations therealong. At least one riser pipe string extends between the wellhead and the platform and includes a plurality of riser pipes engaged end-to-end. In one embodiment of the invention, each riser pipe includes a lower bell-shaped end and an upper spigot-shaped end inserted into the bell-shaped end of the immediately adjacent riser pipe thereabove. The lower bell-shaped end of each riser pipe rests by gravity on and is supported by one of the support plates. In another embodiment of the invention, each riser pipe includes an upper bell-shaped end and a lower spigot-shaped end inserted into the bell-shaped end of the immediately adjacent riser pipe therebelow. The enlarged juncture of the upper bell-shaped end of each riser pipe rests by gravity on and is supported by one of the support plates.

    Abstract translation: 提供了一个提升管组件，用于将海底的海底井口与上表面的平台相互连接。 该组件包括至少一个在井口和平台之间大致延伸的缆线，以为组件提供垂直支撑。 多个支撑板在其上以预定的间隔位置固定到电缆。 至少一个立管管柱在井口和平台之间延伸并且包括端对端地接合的多个立管。 在本发明的一个实施例中，每个提升管包括下部钟形端和插入到其上方的紧邻的立管的钟形端的上部插口端。 每个提升管的下钟形端由重力搁置并由其中一个支撑板支撑。 在本发明的另一个实施例中，每个提升管包括一个上钟形端和一个插入到其下方立即相邻立管的钟形端的下插口端。 每个提升管的上部钟形端的放大的接合点靠重力放置并由一个支撑板支撑。

    Reconfigurable memory with selectable error correction storage
    4.
    发明授权
    Reconfigurable memory with selectable error correction storage 有权
    可重新配置的存储器，具有可选择的纠错存储

    公开(公告)号：US06279072B1

    公开(公告)日：2001-08-21

    申请号：US09359926

    申请日：1999-07-22

    Applicant: Brett L. Williams ,  Donald D. Baldwin

    Inventor： Brett L. Williams ,  Donald D. Baldwin

    IPC: G06F1200

    CPC classification number: G06F11/1052

    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

    Abstract translation: 存储器结构包括分为低阶存储体和高阶存储体的存储器模块。 低阶存储体用作常规存储器。 根据数据的路由，高阶存储体被用作常规存储器或ECC存储器。 在一个实施例中，当高阶存储体用作常规存储器时，来自高阶存储体的数据经由主多路复用器被路由到数据总线。 当高阶存储体用作ECC存储器时，来自辅助部分的数据通过主复用器被路由到纠错电路。 辅助复用器将来自模块的辅助部分的ECC位或主板上的专用ECC存储器组合。 因此，辅助部分补充了板载ECC存储器，以便为需要纠错的错误不耐受应用提供有效的更大的ECC存储器的支持。

    Method and apparatus for enabling access to computer system resources
    5.
    发明授权
    Method and apparatus for enabling access to computer system resources 失效
    允许访问计算机系统资源的方法和装置

    公开(公告)号：US6094702A

    公开(公告)日：2000-07-25

    申请号：US960854

    申请日：1997-10-30

    Applicant: Brett L. Williams ,  Donald D. Baldwin ,  Todd Farrell

    Inventor： Brett L. Williams ,  Donald D. Baldwin ,  Todd Farrell

    IPC: G06F21/00 ,  G06F13/00 ,  G06F12/00

    CPC classification number: G06F21/79

    Abstract: An application-specific integrated circuit (ASIC) for enabling access to memory. ASIC includes a decryptor, a valid authorization storage component, an upgrade verifier, an upgrade storage component, and an enabling component. The decryptor inputs an encrypted authorization code and outputs a decrypted authorization code. The valid authorization storage component stores and outputs a valid authorization code. The upgrade verifier inputs the decrypted authorization code and the valid authorization code, compares the decrypted authorization code to the valid authorization code to determine whether access to the portion of memory is authorized, and outputs a signal to enable access to the portion of memory. The upgrade storage component stores the signal output from the upgrade verifier. The enabling component inputs a memory access signal and a signal stored in the upgrade storage component and outputs a signal indicating whether the portion of memory is enabled.

    Abstract translation: 专用集成电路（ASIC），用于访问存储器。 ASIC包括解密器，有效的授权存储组件，升级验证器，升级存储组件和启用组件。 解密器输入加密的授权码并输出解密的授权码。 有效的授权存储组件存储并输出有效的授权码。 升级验证者输入解密的授权码和有效的授权码，将解密的授权码与有效的授权码进行比较，以确定对存储器部分的访问是否被授权，并输出一个信号，以便访问存储器的一部分。 升级存储组件存储从升级验证器输出的信号。 启用组件输入存储器访问信号和存储在升级存储组件中的信号，并输出指示存储器部分是否被使能的信号。

    Collapsible fuel tank system
    6.
    发明授权
    Collapsible fuel tank system 失效
    可折叠燃油箱系统

    公开(公告)号：US5402968A

    公开(公告)日：1995-04-04

    申请号：US12361

    申请日：1993-02-02

    Applicant: Donald D. Baldwin ,  Randall V. Guest ,  Randall W. Nish ,  Robert G. Pearce

    Inventor： Donald D. Baldwin ,  Randall V. Guest ,  Randall W. Nish ,  Robert G. Pearce

    IPC: B64D37/02

    CPC classification number: B64D37/02 ,  Y02T50/44

    Abstract: A collapsible fuel tank system for use on aircraft and the like includes a plurality of nestable shell sections which, when assembled in proper edgewise orientation, form a shell for the fuel tank. A nose cone and a number of shell-reinforcing bulkheads are axially spaced within the fuel tank and have a ring-and-groove construction for facilitating manual assembly of a fuel tank. A preassembled fuel management system includes an elongated flexible liner encapsulating the bulkheads and having snap connections for quick attachment to the shell interior. All of the components of a plurality of fuel tanks are housed in a single container for shipping and handling purposes.

    Abstract translation: 用于飞机等的可折叠燃料箱系统包括多个可嵌套的壳部分，当以正确的沿边方向组装时，可形成用于燃料箱的壳体。 鼻锥和多个壳加强隔板在燃料箱内轴向间隔开，并具有便于手动组装燃料箱的环槽结构。 预组装的燃料管理系统包括密封舱壁的细长柔性衬套，并且具有用于快速附接到壳体内部的卡扣连接。 多个燃料箱的所有部件都容纳在单个容器中用于运输和处理目的。

    Reconfigurable memory with selectable error correction storage
    7.
    发明授权
    Reconfigurable memory with selectable error correction storage 有权

    公开(公告)号：US06584543B2

    公开(公告)日：2003-06-24

    申请号：US10295661

    申请日：2002-11-14

    Applicant: Brett L. Williams ,  Donald D. Baldwin

    Inventor： Brett L. Williams ,  Donald D. Baldwin

    IPC: G06F1200

    CPC classification number: G06F11/1052

    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

    Reconfigurable memory with selectable error correction storage
    8.
    发明授权
    Reconfigurable memory with selectable error correction storage 有权

    公开(公告)号：US06397290B1

    公开(公告)日：2002-05-28

    申请号：US09932242

    申请日：2001-08-17

    Applicant: Brett L. Williams ,  Donald D. Baldwin

    Inventor： Brett L. Williams ,  Donald D. Baldwin

    IPC: G06F1200

    CPC classification number: G06F11/1052

    Abstract: A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

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