公开(公告)号：KR20100133312A

公开(公告)日：2010-12-21

申请号：KR20100055052

申请日：2010-06-10

Applicant: ELPIDA MEMORY INC

Inventor： AIZAWA KAZUO ,  ASANO ISAMU ,  TOMINAGA JYUNJI ,  KOLOBOV ALEXANDER ,  FONS PAUL ,  SIMPSON ROBERT

IPC: H01L27/115 ,  G11C13/02

CPC classification number: H01L27/2409 ,  H01L27/2454 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/143

Abstract: PURPOSE: A solid-state memory device, a data processing system, and a data processing device thereof are provided to store information by reversibly diversifying a crystalline state. CONSTITUTION: A semiconductor memory device(10) includes an address latch circuit(21) including an address signal(ADD) and a command decoder(22) generating an internal command(ICMD) after decoding a command(CMD). A second interlayer insulating layer has a second through-hole. A recording circuit(26) comprises a reset circuit and a set circuit. A first interlayer insulating layer has a first through-hole.

Abstract translation: 目的：提供固态存储装置，数据处理系统及其数据处理装置，以通过可逆地多样化结晶状态来存储信息。 构成：在解码命令（CMD）之后，半导体存储器件（10）包括地址锁存电路（21），其包括地址信号（ADD）和产生内部命令（ICMD）的命令解码器（22）。 第二层间绝缘层具有第二通孔。 记录电路（26）包括复位电路和设定电路。 第一层间绝缘层具有第一通孔。

公开(公告)号：DE102006041849A1

公开(公告)日：2007-04-12

申请号：DE102006041849

申请日：2006-09-06

Applicant: ELPIDA MEMORY INC

Inventor： ASANO ISAMU ,  SATO NATSUKI ,  NAKAI KIYOSHI

IPC: H01L27/24

公开(公告)号：JP2013157469A

公开(公告)日：2013-08-15

申请号：JP2012017024

申请日：2012-01-30

Applicant: Sharp Corp ,  シャープ株式会社 ,  Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKANO TAKASHI ,  TAMAI YUKIO ,  ASANO ISAMU ,  AIZAWA KAZUO

IPC: H01L27/105 ,  G11C13/00 ,  H01L45/00 ,  H01L49/00

CPC classification number: H01L45/145 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

Abstract: PROBLEM TO BE SOLVED: To provide a variable resistive element capable of performing forming at a low current and a stable switching operation at a low voltage and a low current, and provide a nonvolatile semiconductor storage device with low power consumption and a large capacity by including the variable resistive element.SOLUTION: A variable resistive element 1 holds a variable resistor 13 between a first electrode 14 and a second electrode 12. The variable resistor 13 includes at least two layers of metal oxide or metal oxynitride, a resistance change layer 15 and a high oxygen layer 16. The high oxygen layer 16 is inserted between the first electrode 14 having a work function smaller than that of the second electrode and the resistance change layer 15. An oxygen concentration of the metal oxide is adjusted so that a ratio to a stoichiometric composition of an oxygen composition ratio to a metal element is larger than a ratio to a stoichiometric composition of the oxygen composition ratio to a metal element of the metal oxide constituting the resistance change layer 15.

Abstract translation: 要解决的问题：提供一种能够在低电流和低电流下以低电流进行成形和稳定的开关操作的可变电阻元件，并且通过包括以下方式提供具有低功耗和大容量的非易失性半导体存储器件 可变电阻元件。可变电阻元件1在第一电极14和第二电极12之间保持可变电阻器13.可变电阻器13包括至少两层金属氧化物或金属氮氧化物，电阻变化层15和 高氧层16.高氧层16插入具有小于第二电极和电阻变化层15的功函数的功函数的第一电极14之间。调节金属氧化物的氧浓度，使得与 与金属元素的氧组成比的化学计量组成大于与氧组成的化学计量组成的比率 构成电阻变化层15的金属氧化物的金属元素的比例。

公开(公告)号：JP2012059827A

公开(公告)日：2012-03-22

申请号：JP2010200004

申请日：2010-09-07

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： KAKEGAWA TOMOYASU ,  ASANO ISAMU ,  KAWAGOE TAKESHI ,  SASAOKA HIROMI ,  HYUGANO NAOYA ,  WATANABE YUTA

IPC: H01L27/105 ,  H01L21/768 ,  H01L23/522 ,  H01L27/10 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a higher heat generation efficiency and reducing a rewriting current by covering the circumference of a phase change recording element with a vacuum air gap part with a low conductivity.SOLUTION: A semiconductor device has: a semiconductor substrate; an element layer including a switching element formed on the semiconductor substrate; a phase change recording element 10 configured by laminating a heater electrode 11 connected to the switching element, a phase change recording material layer 12 that changes a phase by heat from the heater electrode 11, and an upper electrode 13 on the element layer sequentially; an interlayer insulating film 21b laminated on the phase change recording element 10; and a vacuum air gap part 15 provided between the element layer and the interlayer insulating film 21b, and formed in the circumference of any one or both of the heater electrode 11 and the phase change recording material layer 12.

Abstract translation: 解决的问题：提供一种能够通过用低导电率的真空气隙部分覆盖相变记录元件的圆周来获得更高的发热效率并减少重写电流的半导体器件。 解决方案：半导体器件具有：半导体衬底; 元件层，包括形成在所述半导体衬底上的开关元件; 通过层叠连接到开关元件的加热电极11，相继改变来自加热电极11的热相的相变记录材料层12和元件层上的上电极13而构成的相变记录元件10; 叠层在相变记录元件10上的层间绝缘膜21b; 以及设置在元件层和层间绝缘膜21b之间并且形成在加热电极11和相变记录材料层12中的任一个或两个的圆周中的真空气隙部分15.权利要求：（C ）2012，JPO＆INPIT

公开(公告)号：JP2011216768A

公开(公告)日：2011-10-27

申请号：JP2010085140

申请日：2010-04-01

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： HYUGANO NAOYA ,  ASANO ISAMU

IPC: H01L27/105 ,  H01L45/00

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method and a structure increasing the current density of a heater unit by reducing the number of steps, in a semiconductor device with a phase-change memory storing information by heating a phase-change material layer by a heater electrode to change a resistance value.SOLUTION: An opening which is the same in shape as an upper surface of the heater electrode 10 and through which the entire surface is exposed is formed in an interlayer insulating film 13 covering the heater electrode 10, a side wall 15 made of an insulating material is formed in the opening, the phase-change material layer 16 is in contact with the heater electrode 10 in the opening with the side wall 10 formed, and a phase-change region 18 in the phase-change material layer 16 is formed in the opening surrounded by the side wall 10.

Abstract translation: 要解决的问题：为了提供通过减少步骤数来增加加热器单元的电流密度的制造方法和结构，在具有相变存储器的半导体器件中，通过将相变材料层加热来存储信息 加热器电极以改变电阻值。解决方案：在覆盖加热器电极10的层间绝缘膜13中形成与加热器电极10的上表面形状相同并且整个表面暴露于该开口的开口， 在开口部形成有由绝缘材料制成的侧壁15，相变材料层16与形成有侧壁10的开口中的加热器电极10接触，并且相变材料层16中的相变区域18， 改变材料层16形成在由侧壁10包围的开口中。

公开(公告)号：JP2010282989A

公开(公告)日：2010-12-16

申请号：JP2009132701

申请日：2009-06-02

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： KAWAGOE TAKESHI ,  ASANO ISAMU

IPC: H01L27/105 ,  H01L27/10 ,  H01L45/00

CPC classification number: H01L27/11517 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

Abstract: PROBLEM TO BE SOLVED: To enhance the integration degree of a semiconductor storage apparatus using a diode as a selecting element, and to reduce a leakage current caused by crystal defect.
SOLUTION: A semiconductor storage apparatus has: impurity diffusion layers 103 and 104 that are a part of a semiconductor substrate 100, and function as one of and the other of an anode and a cathode of a pn junction diode, respectively; a recording layer PC connected to the impurity diffusion layer 104; and a cylindrical side wall insulating film 106 provided on the impurity diffusion layer 103. At least a part of the impurity diffusion layer 104 and at least a part of the recording layer PC are formed in a region surrounded by the side wall insulating film 106. According to this invention, since the pillar-shaped pn junction diode and the recording layer PC are formed in a self-aligned manner, the integration degree can be enhanced. In addition, a silicon pillar is a part of the semiconductor substrate, a leakage current caused by crystal defect is reduced.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提高使用二极管作为选择元件的半导体存储装置的集成度，并且减少由晶体缺陷引起的漏电流。 解决方案：半导体存储装置具有：分别作为半导体衬底100的一部分的杂质扩散层103和104，并且分别用作pn结二极管的阳极和阴极之一和另一个; 连接到杂质扩散层104的记录层PC; 以及设置在杂质扩散层103上的圆筒形侧壁绝缘膜106.至少一部分杂质扩散层104和记录层PC的至少一部分形成在由侧壁绝缘膜106包围的区域中。 根据本发明，由于柱状pn结二极管和记录层PC以自对准的方式形成，因此可以提高积分度。 此外，硅柱是半导体衬底的一部分，由晶体缺陷引起的漏电流减小。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009206418A

公开(公告)日：2009-09-10

申请号：JP2008049751

申请日：2008-02-29

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： SEKO AKIYOSHI ,  SATO NATSUKI ,  ASANO ISAMU

IPC: H01L27/105 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1675

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a nonvolatile memory device which has a variable resistance material of a shape having a narrow part.
SOLUTION: In the method of manufacturing a nonvolatile memory device, information is stored or erased by applying a voltage pulse to a memory section which includes two electrodes 1, 3 and a variable resistance material 2 located between the two electrodes to vary the electric resistance of the variable resistance material. The memory device manufacturing method includes a step of forming a narrow part having a site parallel to the surface between the electrode 1, 3 and smaller than a contact surface area with the variable resistance material 2 by isotropic dry etching.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造具有具有窄部分形状的可变电阻材料的非易失性存储器件的方法。 解决方案：在制造非易失性存储器件的方法中，通过向包括两个电极1,3和位于两个电极之间的可变电阻材料2的存储器部分施加电压脉冲来存储或擦除信息，以改变 可变电阻材料的电阻。 存储器件制造方法包括通过各向同性干蚀刻形成具有与电极1,3之间的表面平行的位置并且小于与可变电阻材料2的接触表面积的位置的窄部分的步骤。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009099854A

公开(公告)日：2009-05-07

申请号：JP2007271428

申请日：2007-10-18

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： SEKO AKIYOSHI ,  SATO NATSUKI ,  ASANO ISAMU

IPC: H01L27/105 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a variable resistance memory device which allows lower electrodes to be formed in a finer size, in which the problem is solved that it is necessary to decrease a contact area between each of the lower electrodes and a variable resistor material to reduce power consumption in the variable resistance memory device.
SOLUTION: The method of manufacturing the variable resistance memory device is characterized by lower electrodes each having the same or smaller size than a lithography-processable size by forming a sidewall made of insulating material on a sidewall of each opening to narrow the diameter of the opening.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造可变电阻存储器件的方法，其允许以更细的尺寸形成下电极，其中解决了需要减少每个电极之间的接触面积的问题 下电极和可变电阻材料，以降低可变电阻存储器件的功耗。 解决方案：制造可变电阻存储器件的方法的特征在于，通过在每个开口的侧壁上形成由绝缘材料制成的侧壁以使直径变窄的每个具有与光刻可加工尺寸相同或更小的尺寸的下电极 的开幕。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007129199A

公开(公告)日：2007-05-24

申请号：JP2006264381

申请日：2006-09-28

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ASANO ISAMU ,  LOWREY TYLER A

IPC: H01L27/105 ,  H01L45/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

Abstract: PROBLEM TO BE SOLVED: To enhance the heat generating efficiency of a non-volatile memory element provided with a recording layer containing a phase changing material.
SOLUTION: The memory element is provided with a bottom electrode 12; a bit line 14 provided on the bottom electrode 12; and the recording layer 15 containing the phase changing material and connecting the bottom electrode 12 to the bit line 14. The bit line 14 has a stereoscopic structure that is in contact with a film formation initiation surface 15a of the recording layer 15. This structure can decrease the area of contact between the recording layer 15 and the bit line 14, and can decrease heat dissipated to the bit line 14, without increasing the film thickness of the recording layer 15. Furthermore, by employing this stereoscopic structure, a top electrode provided in between the bit line 14 and the recording layer 15 can be omitted, and in this case, the process becoming complex can be suppressed.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提高设置有包含相变材料的记录层的非易失性存储元件的发热效率。 存储元件设置有底部电极12; 设置在底部电极12上的位线14; 以及包含相变材料并将底部电极12连接到位线14的记录层15.位线14具有与记录层15的成膜起始表面15a接触的立体结构。该结构可以 减小记录层15和位线14之间的接触面积，并且可以减少散射到位线14的热量，而不增加记录层15的膜厚度。此外，通过采用该立体结构，提供了顶部电极 在位线14和记录层15之间可以省略，在这种情况下，可以抑制过程变得复杂。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007019305A

公开(公告)日：2007-01-25

申请号：JP2005200054

申请日：2005-07-08

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ASANO ISAMU ,  KAWAGOE TAKESHI

IPC: H01L27/105 ,  H01L45/00

CPC classification number: H01L27/2472 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

Abstract: PROBLEM TO BE SOLVED: To solve a problem in a semiconductor storage device utilizing a chalcogenide layer as a storage element that the chalcogenide layer is sublimated when an upper wire is connected on the upper surface of the chalcogenide layer. SOLUTION: In the structure, the chalcogenide layer is not allocated under a connecting part for connecting the upper electrode wire connected to the chalcogenide layer to the other wiring layers. Owing to the structure explained above, it can be prevented that the chalcogenide layer is lost because it is sublimated when a metal is embedded to a connecting hole. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了解决在硫族化物层上表面上连接有硫属化物层时，利用硫族化物层作为存储元件的半导体存储装置的问题。 解决方案：在该结构中，硫族化物层不分配在用于将连接到硫族化物层的上电极线连接到其它布线层的连接部分下。 由于上述结构，可以防止当金属嵌入到连接孔中时，由于升华而硫属元素化层失去。 版权所有（C）2007，JPO＆INPIT