公开(公告)号：WO1984000222A1

公开(公告)日：1984-01-19

申请号：PCT/US1983000985

申请日：1983-06-29

Applicant: ELXSI

Inventor： ELXSI ,  HOLLY, Kenneth ,  SMITH, Gehrard, Jim

IPC: G06F03/04

CPC classification number: G06F13/26 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4217

Abstract: A data bus system utilizing logical transfer channels provides high data rates (even over long distances) and good error detection. The basic function of a transfer channel is to enable temporary assignment of some portion of the bus resource to a specific device and then to allow simple, quick addressing of that device by reference to that channel. There are a relatively small number of transfer channels (say four) that may be attached or detached by the channel processor (IOCP) to meet the data flow requirements. For a transfer to occur between the IOCP (15) and a device (30a, 30b), the IOCP (15) first effects an "attach" operation to assign the device (30a, 30b) a transfer channel for the duration of the transfer. Thereafter, the IOCP (15) allocates the bus cycles among the currently attached transfer channels according to any desired priority scheme, subject to the constraint that the device on a transfer channel be ready to send or receive data before that transfer channel may be granted cycles.

Abstract translation: 使用逻辑传输通道的数据总线系统提供高数据速率（甚至长距离）和良好的错误检测。 传输信道的基本功能是使总线资源的一部分临时分配给特定设备，然后通过参考该信道来允许对该设备的简单，快速寻址。 通道处理器（IOCP）可能连接或分离的传输通道（例如四个）数量相对较少，以满足数据流要求。 为了在IOCP（15）和设备（30a，30b）之间发生转移，IOCP（15）首先进行“附加”操作，以在传送期间分配设备（30a，30b）传输信道 。 此后，IOCP（15）根据任何期望的优先权方案在当前附加的传输信道之间分配总线周期，受限于传输信道上的设备准备好在该传输信道被授予周期之前发送或接收数据 。

公开(公告)号：WO1984000219A1

公开(公告)日：1984-01-19

申请号：PCT/US1983000986

申请日：1983-06-29

Applicant: ELXSI

Inventor： ELXSI ,  SMITH, Gehrard, Jim ,  HOLLY, Kenneth

IPC: G06F03/00

CPC classification number: G06F13/4217

Abstract: Fully synchronous operation is provided by the use of separate frame and clock signals in each of the two directions relative to the I/O Channel Processor (15), with all these signals controlled by the IOCP (15). The transmit (outbound) clock and frame signals (TCLK and TFRM) are simply sent on two lines (25 and 27) from the IOCP (15) to bus terminators (31 and 32) at the far end with peripheral devices (30a and 30b) connecting to these lines (25 and 27) in parallel. The receive (inbound) clock and frame signals (RCLK and RFM) also originate at the IOCP (15), but their lines (25 and 27) go directly to the far end (31 and 32) where they are turned around and sent back to the IOCP (15) with the peripheral devices (30a and 30b) being coupled to these lines (25 and 27) in the reverse sequence. This provides a pair of signals that travel toward the IOCP (15) but one still controlled by the IOCP (15) for timing the incoming data.

公开(公告)号：WO1983002521A1

公开(公告)日：1983-07-21

申请号：PCT/US1983000039

申请日：1983-01-12

Applicant: ELXSI

Inventor： ELXSI ,  HOLBERT, Kenneth, Wayne ,  MASSEY, Edwin, Michael

IPC: H01B07/08

CPC classification number: H02G5/005 ,  H05K1/0263 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/044 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09845 ,  H05K2201/10272

Abstract: A backplane power distribution system for making connections to the power planes of a computer system and having the capability of handling very high levels of current. This is achieved with a stepped backplane construction (17b-e). For example, in a multiple layer system having, in order, a first conductive layer (10a), a first dielectric layer (12a, 12b), a second conductive layer (10b), a second dielectric layer (12bc), and so on, each successive conductive and dielectric layers extend transversely beyond the preceding layers to present a substantial exposed area on all but the first conductive layer (17b-e). Typically, rectangular metal bus bars (not shown) are bolted to the backplane using plated through holes (20b-e) to make contact with the exposed areas (17b-e). Holes through the layers are provided and prepared such that each hole (15, 20 and 22) may make contact with a particular conductive layer as desired or in the case of ground with all ground conductive layers. Conductive layers (10a) and (10i) may be used as signal layers utilizing traces (14) and holes (15) while layers (10b-h) are so-called power planes.

Abstract translation: 背板配电系统，用于连接到计算机系统的电力平面，并且具有处理非常高水平的电流的能力。 这是通过阶梯式背板结构（17b-e）实现的。 例如，在依次具有第一导电层（10a），第一介电层（12a，12b），第二导电层（10b），第二介电层（12bc）等）的多层系统中 ，每个连续的导电和电介质层横向延伸超过先前的层，以在除第一导电层（17b-e）之外的所有部分上呈现基本的暴露区域。 通常，使用电镀通孔（20b-e）将矩形金属汇流条（未示出）螺栓连接到背板以与暴露区域（17b-e）接触。 提供并准备穿过这些层的孔，使得每个孔（15,20和22）可根据需要与特定的导电层接触，或者在所有接地导电层接地的情况下。 导电层（10a）和（10i）可以用作利用迹线（14）和孔（15）的信号层，而层（10b-h）是所谓的电源层。

公开(公告)号：WO1983001544A1

公开(公告)日：1983-04-28

申请号：PCT/US1982001481

申请日：1982-10-19

Applicant: ELXSI

Inventor： ELXSI ,  McFARLAND, Harold, L., Jr. ,  LAU, Harlan ,  ROBERTS, Allen, W.

IPC: H04B03/02

CPC classification number: G06F13/40 ,  G06F13/4217 ,  H03F3/45071 ,  H03K5/02

Abstract: A high speed data bus system for communication among various functional units (10). The functional units are mounted in immediately adjacent connectors (25) on the backplane (Fig. 4) to define a populated section of effective characteristic impedance Z0' and one or two unpopulated sections of impedance Z0. A populated end of the transmission line (40) is resistively terminated with a resistance corresponding to Z0' (65) while the unpopulated end is terminated with a resistance corresponding to Z0 (67). The border between the populated and unpopulated sections is terminated with a resistance corresponding to 1/(1Z0'-1/Z0) (68), thus eliminating signal reflections. Driver gating circuitry (Fig. 9B) responsive to first and second data input signals, an enable signal, and a conditional inversion input signal performs multiple levels of gating with minimum of propagation delay. The preferred differential receiver (Fig. 10B) amplifies a relatively low level differential input signal and performs an exclusive OR function with a conditional inversion signal. To implement the indivisibility of transfers the control logic for each port includes screening circuitry (190) responsive to the state of the port's buffers (180), and further responsive to flags from the functional unit for selectively accepting or rejecting bus information, and further includes screening constraint circuitry (230) ensure that the port accepts all or none of the information that makes up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers.

Abstract translation: 一种用于各功能单元（10）之间通信的高速数据总线系统。 功能单元安装在背板上的紧邻的连接器（25）上（图4），以定义有效特性阻抗Z0'和阻抗Z0的一个或两个未占用部分的填充部分。 传输线（40）的填充端通过对应于Z0'（65）的电阻被电阻端接，而未占用端以具有对应于Z0（67）的电阻终止。 人口稠密和未填充部分之间的边界以对应于1 /（1Z0'-1 / Z0）（68）的电阻终止，从而消除信号反射。 响应于第一和第二数据输入信号的驱动器选通电路（图9B），使能信号和条件反转输入信号以最小的传播延迟执行多级选通。 优选的差分接收机（图10B）放大相对较低电平的差分输入信号，并用条件反转信号执行异或功能。 为了实现传输的不可分割性，每个端口的控制逻辑包括响应于端口缓冲器（180）的状态的屏蔽电路（190），并且还响应于来自功能单元的标志来选择性地接收或拒绝总线信息，并且还包括 筛选约束电路（230）确保端口接受组成传输的所有信息或无信号。 根据标志，拒绝可能是总计，或者可能仅适用于指定类别的转移。