Abstract:
In an ion bean acceleration system, transient electrical arc suppression and ion beam accelerator biasing circuitry. Two-terminal circuitry, connectable in series, for suppressing arcs by automatically sensing arc conditions and switch from at least a first operating state providing a relatively low resistance electrical pathway for current between source and load terminals to at least a second, relatively high resistance electrical pathway. Selection of circuit component characteristics permits controlling the delay in returning from the second state to the first state after the arc has been suppressed.