公开(公告)号：US20180130924A1

公开(公告)日：2018-05-10

申请号：US15800537

申请日：2017-11-01

Applicant: EPISTAR CORPORATION

Inventor： Chun-Teng Ko ,  Chao-Hsing Chen ,  Jia-Kuen Wang ,  YEN-LIANG KUO ,  Chih-Hao Chen ,  Wei-Jung Chung ,  Chih-Ming Wang ,  Wei-Chih Peng ,  Schang-Jing Hon ,  YU-YAO LIN

IPC: H01L33/22 ,  H01L33/38 ,  H01L33/46 ,  H01L33/62 ,  H01L33/00

CPC classification number: H01L33/22 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32 ,  H01L33/38 ,  H01L33/46 ,  H01L33/62

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a surrounding exposed region formed on peripheries of the semiconductor stack, exposing a surface of the first semiconductor layer; a conductive layer formed on the second semiconductor layer, including a first conductive region extending toward and contacting the surface of the first semiconductor layer in the surrounding exposed region; an electrode layer formed on the surrounding exposed region, surrounding the semiconductor stack, contacting the conductive layer and including an electrode pad not overlapping the semiconductor stack; an outside insulating layer covering a portion of the conductive layer and the electrode layer, including a first opening exposing the other portion of the conductive layer; a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the first opening; and a conductive substrate.

公开(公告)号：US20140117306A1

公开(公告)日：2014-05-01

申请号：US13661556

申请日：2012-10-26

Applicant: EPISTAR CORPORATION

Inventor： YU-YAO LIN ,  Yen-Chih Chen ,  Chien-Yuan Tseng ,  Tsun-Kai Ko ,  Chun-Ta Yu ,  Shih-Chun Ling ,  Cheng-Hsiung Yen ,  Hsin-Hsien Wu

IPC: H01L33/04

CPC classification number: H01L33/04 ,  H01L33/12 ,  H01L33/32

Abstract: A light-emitting device comprises a first type semiconductor layer, a multi-quantum well structure on the first type semiconductor layer, and a second type semiconductor layer on the multi-quantum well structure, wherein the multi-quantum well structure comprises a first portion near the first type semiconductor layer, a second portion near the second type semiconductor layer, and a strain releasing layer between the first portion and the second portion and comprising a first layer including Indium, a second layer including Aluminum on the first layer, and a third layer including Indium on the second layer, wherein the Indium concentration of the third layer is higher than that of the first layer.

Abstract translation: 发光器件包括第一类型半导体层，第一类型半导体层上的多量子阱结构和多量子阱结构上的第二类型半导体层，其中多量子阱结构包括第一部分 靠近第一类型半导体层，靠近第二类型半导体层的第二部分和在第一部分和第二部分之间的应变释放层，并且包括包括铟的第一层，在第一层上包括铝的第二层和 第三层包括第二层上的铟，其中第三层的铟浓度高于第一层的铟浓度。

公开(公告)号：US20140167097A1

公开(公告)日：2014-06-19

申请号：US14104017

申请日：2013-12-12

Applicant: EPISTAR CORPORATION

Inventor： HSIN-HSIEN WU ,  YU-YAO LIN ,  YEN-CHIH CHEN ,  CHIEN-YUAN TSENG ,  CHUN-TA YU ,  CHENG-HSIUNG YEN ,  SHIH-CHUN LING ,  TSUN-KAI KO ,  DE-SHAN KUO

IPC: H01L33/24

CPC classification number: H01L33/0095 ,  H01L33/025 ,  H01L33/16 ,  H01L33/22 ,  H01L33/28 ,  H01L33/30

Abstract: A method of fabricating an optoelectronic device comprising, providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a semiconductor epitaxial stack on the first major surface including a first conductive-type semiconductor layer having a first doping concentration, an active layer, and a second conductive-type semiconductor layer wherein the semiconductor epitaxial stack having four boundaries and a geometric center; and forming a plurality of the hollow components in the first conductive-type semiconductor layer wherein the plurality of the hollow components is formed from the boundary of the semiconductor epitaxial stack to the geometric center of the semiconductor epitaxial stack.

Abstract translation: 一种制造光电器件的方法，包括：提供衬底，其中所述衬底包括与所述第一主表面相对的第一主表面和第二主表面; 在所述第一主表面上形成包括具有第一掺杂浓度的第一导电型半导体层，有源层和第二导电型半导体层的半导体外延堆叠，其中所述半导体外延堆叠具有四个边界和几何中心; 以及在所述第一导电型半导体层中形成多个所述中空部件，其中所述多个所述中空部件由所述半导体外延叠层的边界形成为所述半导体外延叠层的几何中心。