BATCH-WISE HANDLING OF SIGNALS IN A PROCESSING SYSTEM

    公开(公告)号:CA2350517C

    公开(公告)日:2008-05-20

    申请号:CA2350517

    申请日:1999-11-12

    Abstract: The present invention relates to multiprocessing systems in which signals o r processes are scheduled in order of their priority level. The invention is based on batch-wise acceptance and scheduling of job signals, and utilizes at least one delay queue (20) for temporarily storing job signals to the processing system before they are accepted for scheduling. The processing system further comprises circuitry (25) for batch - wise insertion of the temporarily stored job signals into the job scheduler (30) of the multiprocessing system. In this way, the utilization of the parallel processing units (45A-D) is increased and the number of changes between different priority levels in the multiprocessing system is minimized.

    A JOB-PARALLEL PROCESSOR
    4.
    发明专利

    公开(公告)号:CA2350921A1

    公开(公告)日:2000-05-25

    申请号:CA2350921

    申请日:1999-11-12

    Abstract: The invention generally relates to a processor developed for a service netwo rk that provides various services to a plurality of users connected to the network. The processor (30; 50) comprises a job queue (52) with a number of storage positions for storing job signals corresponding to jobs that form pa rt of substantially independent services requested by the users of the network, and a plurality of parallel processing units (54) which independently proces s job signals from different storage positions of the job queue (52) to execut e corresponding jobs in parallel. As a number of jobs are executed speculatively, a unit (56) for checking for possible dependencies between th e executed jobs is incorporated into the processor. If a dependency is detecte d for a speculative job, that job is flushed. To ensure prompt and proper service for the users of the service network, flushed jobs are quickly restarted directly from the job queue.

    5.
    发明专利
    未知

    公开(公告)号:NO171336C

    公开(公告)日:1993-02-24

    申请号:NO872387

    申请日:1987-06-05

    Abstract: A method and apparatus for determining what programme shall utilise a rapid access memory in a computer working with a plurality of programmes and having a conventional slow access (NM) memory and a rapid access memory (CM), characterized in that during a test period there registered for each programme the number of instructions in the programme requiring access to the memory, this number being divided by the whole memory space required by a programme, the quotients formed after each other in this way being compared with each other and for the programme with the highest quotient the memory content is transferred from the slow access memory to the rapid access memory. For each programme there is registered with the aid of a counter means (RF) the number of instructions requiring access to the slow access memory (NM). This number is divided with the aid of a measuring circuit (R1, R2, JR, KB) by the entire memory space for the respective programme noted in a space memory (SM). For the programme with the highest quotient the memory content is transferred from the relatively slow access memory (NM) to the rapid access memory (CM). An address memory (AM) is arranged, and for the programme information transferred from the slow access memory (NM) to the rapid access memory (CM) the address memory reads out the starting address of the programme information in the rapid access memory (CM) on addressing a starting address in the slow access memory (NM)>

    METHOD AND APPARATUS FOR DETERMINING IN A COMPUTER WHICH OF A NUMBER OF PROGRAMMES ARE ALLOWED TO UTILISE A RAPID ACCESS MEMORY

    公开(公告)号:GR3000766T3

    公开(公告)日:1991-10-10

    申请号:GR900400623

    申请日:1990-09-07

    Abstract: A method and apparatus for determining what programme shall utilise a rapid access memory in a computer working with a plurality of programmes and having a conventional slow access (NM) memory and a rapid access memory (CM), characterized in that during a test period there registered for each programme the number of instructions in the programme requiring access to the memory, this number being divided by the whole memory space required by a programme, the quotients formed after each other in this way being compared with each other and for the programme with the highest quotient the memory content is transferred from the slow access memory to the rapid access memory. For each programme there is registered with the aid of a counter means (RF) the number of instructions requiring access to the slow access memory (NM). This number is divided with the aid of a measuring circuit (R1, R2, JR, KB) by the entire memory space for the respective programme noted in a space memory (SM). For the programme with the highest quotient the memory content is transferred from the relatively slow access memory (NM) to the rapid access memory (CM). An address memory (AM) is arranged, and for the programme information transferred from the slow access memory (NM) to the rapid access memory (CM) the address memory reads out the starting address of the programme information in the rapid access memory (CM) on addressing a starting address in the slow access memory (NM)>

    8.
    发明专利
    未知

    公开(公告)号:DK325187A

    公开(公告)日:1987-12-27

    申请号:DK325187

    申请日:1987-06-25

    Abstract: A method and apparatus for determining what programme shall utilise a rapid access memory in a computer working with a plurality of programmes and having a conventional slow access (NM) memory and a rapid access memory (CM), characterized in that during a test period there registered for each programme the number of instructions in the programme requiring access to the memory, this number being divided by the whole memory space required by a programme, the quotients formed after each other in this way being compared with each other and for the programme with the highest quotient the memory content is transferred from the slow access memory to the rapid access memory. For each programme there is registered with the aid of a counter means (RF) the number of instructions requiring access to the slow access memory (NM). This number is divided with the aid of a measuring circuit (R1, R2, JR, KB) by the entire memory space for the respective programme noted in a space memory (SM). For the programme with the highest quotient the memory content is transferred from the relatively slow access memory (NM) to the rapid access memory (CM). An address memory (AM) is arranged, and for the programme information transferred from the slow access memory (NM) to the rapid access memory (CM) the address memory reads out the starting address of the programme information in the rapid access memory (CM) on addressing a starting address in the slow access memory (NM)>

    9.
    发明专利
    未知

    公开(公告)号:NO872387D0

    公开(公告)日:1987-06-05

    申请号:NO872387

    申请日:1987-06-05

    Abstract: A method and apparatus for determining what programme shall utilise a rapid access memory in a computer working with a plurality of programmes and having a conventional slow access (NM) memory and a rapid access memory (CM), characterized in that during a test period there registered for each programme the number of instructions in the programme requiring access to the memory, this number being divided by the whole memory space required by a programme, the quotients formed after each other in this way being compared with each other and for the programme with the highest quotient the memory content is transferred from the slow access memory to the rapid access memory. For each programme there is registered with the aid of a counter means (RF) the number of instructions requiring access to the slow access memory (NM). This number is divided with the aid of a measuring circuit (R1, R2, JR, KB) by the entire memory space for the respective programme noted in a space memory (SM). For the programme with the highest quotient the memory content is transferred from the relatively slow access memory (NM) to the rapid access memory (CM). An address memory (AM) is arranged, and for the programme information transferred from the slow access memory (NM) to the rapid access memory (CM) the address memory reads out the starting address of the programme information in the rapid access memory (CM) on addressing a starting address in the slow access memory (NM)>

    Improved result handling in a multiprocessing system

    公开(公告)号:AU1437200A

    公开(公告)日:2000-06-05

    申请号:AU1437200

    申请日:1999-11-12

    Abstract: In general, the invention is directed towards a multiprocessing system in which jobs are speculatively executed in parallel by multiple processors (30-1, 30-2, ..., 30-N). By speculating on the existence of more coarse-grained parallelism, so-called job-level parallelism, and backing of to sequential execution only in cases where dependencies that prevent parallel execution of jobs are detected, a high degree of parallelism can be extracted. According to the invention a private memory buffer is speculatively allocated for holding results, such as a communication message, an operation system call or a new job signal, of a speculatively executed job, and these results are speculatively written directly into the allocated memory buffer. When commit priority is assigned to the speculatively executed job, a pointer referring to the allocated memory buffer is transferred to an input/output (10) device which may access the memory buffer by means of the transferred pointer. In this way, by speculatively writing messages and signals into private memory buffers, even further parallelism can be extracted.

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