公开(公告)号：WO0017755A2

公开(公告)日：2000-03-30

申请号：PCT/SE9901673

申请日：1999-09-23

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS

IPC: G06F11/20 ,  G06F11/14 ,  G06F12/00 ,  G06F15/177

CPC classification number: G06F11/1451 ,  Y10S707/99931

Abstract: A fault-tolerant client-server system has a primary server, a backup server; and a client. The client sends a request to the primary server, which receives and processes the request, including sending the response to the client, independent of any backup processing. The response includes the primary server state information. The primary server also performs backup processing that includes periodically sending the primary server state information to the backup server. The client receives the response from the primary server, and sends the primary server state information to the backup server. The primary server state information includes all request-reply pairs that the primary server has handled since a most recent transmission of primary server state information from the primary server to the backup server. The primary server's means for performing backup processing may be activated periodically based on a predetermined time interval. Alternatively, it may be activated when the primary server's memory for storing the primary server state information is filled to a predetermined amount.

Abstract translation: 容错客户端 - 服务器系统具有主服务器，备份服务器; 和客户端。 客户端向主服务器发送请求，该主服务器接收并处理请求，包括将响应发送到客户端，而与任何备份处理无关。 响应包括主服务器状态信息。 主服务器还执行备份处理，包括定期将主服务器状态信息发送到备份服务器。 客户端从主服务器接收响应，并将主服务器状态信息发送到备份服务器。 主服务器状态信息包括主服务器自主服务器状态信息从主服务器到备份服务器的最新传输之后所处理的所有请求 - 回复对。 可以基于预定的时间间隔周期性地激活用于执行备份处理的主服务器的装置。 或者，当用于存储主服务器状态信息的主服务器的存储器被填充到预定量时，可以激活它。

公开(公告)号：WO0004449A2

公开(公告)日：2000-01-27

申请号：PCT/SE9901062

申请日：1999-06-15

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS ,  HALVORSSON DAN OLOV ,  JONSSON TOMAS

IPC: G06F11/277 ,  G06F11/26

CPC classification number: G06F11/27

Abstract: The present invention relates to a fault testing in digital systems and devices therefor. A processor unit (2) is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyser (3) is activated and the processor unit (2) generates a set of stimuli, influencing the appropriate logical units. The output response analyser (3) collects responses of the stimuli at different nodes (13) in the digital system (1) and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. Preferably, the present state of the processor (2) and other logical units are stored in a storage means (15) prior to the test and recovered after the testing is finished. The invention functions both at chip and board levels, and on systems with several units.

Abstract translation: 本发明涉及数字系统及其设备中的故障测试。 处理器单元（2）可从其他活动中获得，并且待测试的逻辑单元被设置为预定状态。 输出响应分析器（3）被激活，并且处理器单元（2）产生一组刺激，影响适当的逻辑单元。 输出响应分析器（3）收集数字系统（1）中不同节点（13）处的刺激的响应并从它们创建签名。 信号经过验证，如果发现故障，则会发现此错误。 优选地，处理器（2）和其他逻辑单元的当前状态在测试之前被存储在存储装置（15）中并且在测试完成之后被恢复。 本发明在芯片和电路板级以及具有多个单元的系统上起作用。

公开(公告)号：WO9930235A3

公开(公告)日：1999-08-26

申请号：PCT/SE9802267

申请日：1998-12-09

Applicant: ERICSSON TELEFON AB L M

Inventor： ROSENDAHL MICHAEL ,  JONSSON TOMAS LARS ,  HOLMBERG PER ANDERS

IPC: G06F11/10 ,  G06F11/16 ,  G06F11/18 ,  G06F11/14

CPC classification number: G06F11/1654 ,  G06F11/1641 ,  G06F11/165

Abstract: The present invention relates to a method of utilizing information made available in a bit error check of data words belonging to instructions read into a processor having a first (11) and a second (11') calculating unit which operate in parallel with one another, a so-called double processor mode. The processor structure also comprises a third and a fourth calculating unit (13, 13') intended for continuously checking for possible bit errors in read-in data words, a comparator (14) for comparing output data from parallel operating units (11, 11'), a diagnostic unit (15) adapted to determine which of the calculating units delivered correct output data when detecting a difference in output data in the comparator (14), and a control unit (16) adapted to control that the output data from the processor structure (1) originates from a calculating unit that has delivered correct output data. The processor switches to a single processor mode when a difference in output data is detected in the comparator. The data words are read directly into respective calculating units (11, 11') without correction for possible bit errors when the processor operates in a double processor mode, and the information from the third and fourth calculating units (13, 13') is used to effect said determination in the diagnostic unit (15). Bit error control and bit error correction are used in a known manner when the processor operates in a single processor mode.

Abstract translation: 本发明涉及利用在具有读取到具有彼此并行操作的第一（11）和第二（11'）计算单元的处理器中的指令的数据字的位错误校验中获得的信息的方法， 一种所谓的双处理器模式。 处理器结构还包括用于连续检查读入数据字中可能的比特错误的第三和第四计算单元（13,13'），比较器（14），用于比较来自并行操作单元（11,11）的输出数据 '），诊断单元（15），其适于在检测到所述比较器（14）中的输出数据的差异时确定传送出的正确输出数据中的哪个计算单元;以及控制单元（16），其适于控制所述输出数据 处理器结构（1）源自已传送正确输出数据的计算单元。 当在比较器中检测到输出数据的差异时，处理器切换到单处理器模式。 当处理器以双处理器模式操作时，将数据字直接读取到相应的计算单元（11,11'）中，而不对可能的位错误进行校正，并且使用来自第三和第四计算单元（13,13'）的信息 以在所述诊断单元（15）中进行所述确定。 当处理器以单个处理器模式运行时，位错误控制和位错误校正以已知的方式使用。

公开(公告)号：AU6591001A

公开(公告)日：2001-11-12

申请号：AU6591001

申请日：2001-04-27

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS

IPC: G06F9/38 ,  G06F12/0862 ,  G06F12/08

公开(公告)号：AU1564801A

公开(公告)日：2001-06-06

申请号：AU1564801

申请日：2000-11-10

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS

IPC: G06F12/10

公开(公告)号：AU1437200A

公开(公告)日：2000-06-05

申请号：AU1437200

申请日：1999-11-12

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS ,  KLING LARS-ORJAN ,  JOHNSON STEN EDWARD ,  EGELAND TERJE

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F12/02 ,  G06F13/38

Abstract: In general, the invention is directed towards a multiprocessing system in which jobs are speculatively executed in parallel by multiple processors (30-1, 30-2, ..., 30-N). By speculating on the existence of more coarse-grained parallelism, so-called job-level parallelism, and backing of to sequential execution only in cases where dependencies that prevent parallel execution of jobs are detected, a high degree of parallelism can be extracted. According to the invention a private memory buffer is speculatively allocated for holding results, such as a communication message, an operation system call or a new job signal, of a speculatively executed job, and these results are speculatively written directly into the allocated memory buffer. When commit priority is assigned to the speculatively executed job, a pointer referring to the allocated memory buffer is transferred to an input/output (10) device which may access the memory buffer by means of the transferred pointer. In this way, by speculatively writing messages and signals into private memory buffers, even further parallelism can be extracted.

公开(公告)号：AU1437000A

公开(公告)日：2000-06-05

申请号：AU1437000

申请日：1999-11-12

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS ,  LINNERMARK NILS OLA ,  STROMBERGSON KARL OSCAR JOACHI ,  EGELAND TERJE ,  CARLSSON MAGNUS

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F15/177 ,  G06F15/16

公开(公告)号：AU1436900A

公开(公告)日：2000-06-05

申请号：AU1436900

申请日：1999-11-12

Applicant: ERICSSON TELEFON AB L M

Inventor： HOLMBERG PER ANDERS ,  KLING LARS-ORJAN ,  JOHNSON STEN EDWARD ,  EGELAND TERJE

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F9/52 ,  G06F15/173 ,  G06F15/80 ,  H04Q3/545

Abstract: The invention generally relates to a processor developed for a service network that provides various services to a plurality of users connected to the network. The processor (30; 50) comprises a job queue (52) with a number of storage positions for storing job signals corresponding to jobs that form part of substantially independent services requested by the users of the network, and a plurality of parallel processing units (54) which independently process job signals from different storage positions of the job queue (52) to execute corresponding jobs in parallel. As a number of jobs are executed speculatively, a unit (56) for checking for possible dependencies between the executed jobs is incorporated into the processor. If a dependency is detected for a speculative job, that job is flushed. To ensure prompt and proper service for the users of the service network, flushed jobs are quickly restarted directly from the job queue.

公开(公告)号：CA2350798A1

公开(公告)日：2000-05-25

申请号：CA2350798

申请日：1999-11-12

Applicant: ERICSSON TELEFON AB L M

Inventor： KLING LARS-ORJAN ,  TIKEKAR NIKHIL ,  JOHNSON STEN EDWARD ,  SOHONI MILIND ,  HOLMBERG PER ANDERS

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F9/52 ,  G06F15/173 ,  G06F15/80 ,  H04Q3/545

Abstract: The present invention presents a processing system (1) comprising a number o f memory-sharing processors (10a-e) arranged for parallel processing of jobs, and data consistency means (14) for assuring data consistency. The processin g system (1) comprises a scheduler (17), for scheduling jobs for execution on the processors (10a-e) according to a first algorithm. The processing system (1) according to the present invention further uses means for retiring the jobs (18) in an order given by a second algorithm, preferably according to a global order of creation. The second algorithm is different from the first algorithm. The first algorithm may be adjusted to the particular system used , and may base the scheduling to a particular processor on e.g. the source, target, communication channel or creating processor for the job in question. The processing system (1) uses a common job queue (16), and the scheduling i s preferably performed adaptively.

公开(公告)号：SE9902373D0

公开(公告)日：1999-06-22

申请号：SE9902373

申请日：1999-06-22

Applicant: ERICSSON TELEFON AB L M

Inventor： EGELAND TERJE ,  KLING LARS-OERJAN ,  JOHNSON STEN EDVARD ,  HOLMBERG PER ANDERS

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F12/02 ,  G06F13/38 ,  G06F

Abstract: In general, the invention is directed towards a multiprocessing system in which jobs are speculatively executed in parallel by multiple processors (30-1, 30-2, ..., 30-N). By speculating on the existence of more coarse-grained parallelism, so-called job-level parallelism, and backing of to sequential execution only in cases where dependencies that prevent parallel execution of jobs are detected, a high degree of parallelism can be extracted. According to the invention a private memory buffer is speculatively allocated for holding results, such as a communication message, an operation system call or a new job signal, of a speculatively executed job, and these results are speculatively written directly into the allocated memory buffer. When commit priority is assigned to the speculatively executed job, a pointer referring to the allocated memory buffer is transferred to an input/output (10) device which may access the memory buffer by means of the transferred pointer. In this way, by speculatively writing messages and signals into private memory buffers, even further parallelism can be extracted.