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    AN INSTRUCTION DECODER
    1.
    发明申请
    AN INSTRUCTION DECODER 审中-公开
    指示解码器

    公开(公告)号：WO9928817A3

    公开(公告)日：1999-07-22

    申请号：PCT/SE9802205

    申请日：1998-12-02

    Applicant: ERICSSON TELEFON AB L M ,  ROOS TOBIAS ,  HALVARSSON DAN ,  JONSSON TOMAS

    Inventor： ROOS TOBIAS ,  HALVARSSON DAN ,  JONSSON TOMAS

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F11/30 ,  G06F11/34 ,  G06F9/32

    CPC classification number: G06F9/30181 ,  G06F9/261 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/30196 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3466

    Abstract: In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of the computer, such as a trace enabling signal (63), influencing the translation process in the instruction decoding unit. These state signals (63) are added to the operation code (65) of the program instruction to be decoded, the operation code of the program instruction thus being extended and used as input to a translating table (55), the extended operation code of the program instruction being taken as an address of a field in the table. The addresses and thus the contents of the fields addressed for the same operation code of a program instruction can then be different for different values of the state signals. Thus generally, the state signals cause the instruction decoder to change its translating algorithm so that the decoder can decode an operation code differently depending on the state which the signals adopt. The dynamic decoding can for a trace enabling signal be used for switching on and off a trace function. In the normal case, when tracing is not desired, no microinstructions supporting the trace function have to be executed and thereby the performance and in particular the speed of the computer system will be increased.

    Abstract translation: 在计算机系统中，用于将程序指令转换为微代码指令的指令解码单元动态地进行操作。 因此，单元接收指示影响指令解码单元中的转换处理的计算机的状态的状态信号，例如跟踪使能信号（63）。 这些状态信号（63）被添加到要解码的程序指令的操作代码（65）中，因此程序指令的操作代码被扩展并用作转换表（55）的输入，扩展操作代码 程序指令被视为表中字段的地址。 因此，对于不同的状态信号值，对于程序指令的相同操作代码寻址的字段的地址和因此的内容可以是不同的。 因此，通常情况下，状态信号使指令译码器改变其翻译算法，使得解码器可根据信号采用的状态对不同的操作码进行解码。 动态解码可以用于跟踪启用信号用于打开和关闭跟踪功能。 在正常情况下，当不需要跟踪时，不需要执行支持跟踪功能的微指令，从而提高计算机系统的性能，特别是速度。

    FAULT DETECTION IN DIGITAL SYSTEM
    2.
    发明申请
    FAULT DETECTION IN DIGITAL SYSTEM 审中-公开
    数字系统中的故障检测

    公开(公告)号：WO0004449A2

    公开(公告)日：2000-01-27

    申请号：PCT/SE9901062

    申请日：1999-06-15

    Applicant: ERICSSON TELEFON AB L M

    Inventor： HOLMBERG PER ANDERS ,  HALVORSSON DAN OLOV ,  JONSSON TOMAS

    IPC: G06F11/277 ,  G06F11/26

    CPC classification number: G06F11/27

    Abstract: The present invention relates to a fault testing in digital systems and devices therefor. A processor unit (2) is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyser (3) is activated and the processor unit (2) generates a set of stimuli, influencing the appropriate logical units. The output response analyser (3) collects responses of the stimuli at different nodes (13) in the digital system (1) and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. Preferably, the present state of the processor (2) and other logical units are stored in a storage means (15) prior to the test and recovered after the testing is finished. The invention functions both at chip and board levels, and on systems with several units.

    Abstract translation: 本发明涉及数字系统及其设备中的故障测试。 处理器单元（2）可从其他活动中获得，并且待测试的逻辑单元被设置为预定状态。 输出响应分析器（3）被激活，并且处理器单元（2）产生一组刺激，影响适当的逻辑单元。 输出响应分析器（3）收集数字系统（1）中不同节点（13）处的刺激的响应并从它们创建签名。 信号经过验证，如果发现故障，则会发现此错误。 优选地，处理器（2）和其他逻辑单元的当前状态在测试之前被存储在存储装置（15）中并且在测试完成之后被恢复。 本发明在芯片和电路板级以及具有多个单元的系统上起作用。

    ENHANCED INSTRUCTION DECODING
    3.
    发明申请
    ENHANCED INSTRUCTION DECODING 审中-公开
    增强的指令解码

    公开(公告)号：WO9928818A3

    公开(公告)日：1999-09-16

    申请号：PCT/SE9802210

    申请日：1998-12-02

    Applicant: ERICSSON TELEFON AB L M ,  HALVARSSON DAN ,  JONSSON TOMAS ,  HOLMBERG PER

    Inventor： HALVARSSON DAN ,  JONSSON TOMAS ,  HOLMBERG PER

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/382 ,  G06F9/3802

    Abstract: When decoding instructions of a program to be executed in a central processing unit (9) comprising pipelining facilities for fast instruction decoding, part of the decoding is executed or the decoding in pipelining units is prepared in a remapping unit (5) during loading a program into a program or primary memory (7) used by the central processor, the remapping or predecoding operation resulting in operation codes which can be very rapidly interpreted by the pipelining units of the central processor. Thus, the operation code field of an instruction is changed to include information on e.g. instruction length, jumps, parameters, etc., this information indicating the instruction length, whether it is a jump instruction or has a parameter etc. respectively, in a direct way that allows the use of simple combinatorial circuits in the pipelining units. This makes it possible to obtain a decoding of complex instructions using few clock cycles, and also that old type instructions can be used as input to the system without degrading the time performance of the instruction decoding. Also, accesses of the program memory (7) and a data memory (11) can be made earlier during execution of a program, which saves execution time.

    Abstract translation: 当在包括用于快速指令解码的流水线设施的中央处理单元（9）中执行的程序的指令解码时，在加载程序期间执行部分解码或者在重映射单元（5）中准备流水线单元中的解码 写入由中央处理器使用的程序或主存储器（7）中，重映射或预解码操作产生操作代码，其可由中央处理器的流水线单元非常快速地解释。 因此，指令的操作码字段被改变以包括关于例如 指令长度，跳转，参数等，该信息分别表示指令长度，是跳转指令还是具有参数等，以直接的方式允许在流水线单元中使用简单的组合电路。 这使得可以使用少量时钟周期来获得对复杂指令的解码，并且还可以将旧类型指令用作系统的输入而不降低指令解码的时间性能。 而且，程序存储器（7）和数据存储器（11）的访问可以在执行程序期间提前进行，这节省了执行时间。

    ADJUSTMENT OF PLANNED MOVEMENT BASED ON RADIO NETWORK CONDITIONS
    8.
    发明专利
    ADJUSTMENT OF PLANNED MOVEMENT BASED ON RADIO NETWORK CONDITIONS 未知

    公开(公告)号：CA3008225A1

    公开(公告)日：2016-12-01

    申请号：CA3008225

    申请日：2015-12-14

    Applicant: ERICSSON TELEFON AB L M

    Inventor： WANSTEDT STEFAN ,  JONSSON TOMAS ,  OKVIST PETER ,  ARNGREN TOMMY

    IPC: B64C19/00 ,  G05D1/02 ,  H04W4/02 ,  H04W4/50 ,  H04W72/08

    Abstract: A movement adjusting device adjusts the movement of a wireless transceiver moving according to a plan along a route through a wireless communication network (1o, 12) while communicating for an application having a service requirement on the wireless communication network (10, 2), the wireless communication network (10, 12) comprises cells (14, 16, 8, 20) and the movement adjusting device is operative to: obtain radio network condition data (RSRP, RSRQ) regarding a group of cells (14, 16, 8, 20) comprising a current cell (14) in which the wireless transceiver 10 (28) is located and a number of neighbouring cells (16, 18, 20) into which the wireless transceiver (28) may move, analyse the radio network condition data (RSRQ, RSRP) with regard to fulfilling the service requirement of the application (26), and make an adjustment of the planned movement if the analysis indicates that this would improve on the 1 fulfilling of the service requirement.

    Fault detection in digital system
    9.
    发明专利
    Fault detection in digital system 未知

    公开(公告)号：AU4671299A

    公开(公告)日：2000-02-07

    申请号：AU4671299

    申请日：1999-06-15

    Applicant: ERICSSON TELEFON AB L M

    Inventor： HOLMBERG PER ANDERS ,  HALVORSSON DAN OLOV ,  JONSSON TOMAS

    IPC: G06F11/277 ,  G06F11/26 ,  G01R31/317

    Abstract: For fault testing in a digital system, a processor unit is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyze is activated and the processor unit generates a set of stimuli, influencing the appropriate logical units. The output response analyzer collects responses to the stimuli at different nodes in the digital system and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. The present state of the processor and other logical units are stored in a storage device prior to the test and recovered after the testing is finished. This fault testing can be performed both at chip and board levels, and on systems with several units.

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