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公开(公告)号：DE69621724T2
公开(公告)日：2002-10-02
申请号：DE69621724
申请日：1996-08-20
Applicant: FUJITSU LTD
Inventor： NANTO TOSHIYUKI , NAKAHARA HIROYUKI , AWAJI NORYUKI , WAKITANI MASAYUKI , SHINODA TSUTAE , KONNO KEIICHIRO , YANAGIBASHI YASUO , SAKAMOTO NAOHITO
IPC: H01J9/02 , H01J9/24 , H01J11/14 , H01J11/22 , H01J11/24 , H01J11/28 , H01J11/32 , H01J11/34 , H01J11/36 , H01J11/38 , H01J11/42 , H01J11/44 , H01J17/04 , H01J17/49
Abstract: A surface discharge type plasma display panel (PDP) includes a pair of front and rear substrates (11, 21) with a discharge space (30) therebetween and a plurality of pairs of display electrodes on internal surface of either the front or rear substrate. The display electrodes extend along each display line L. The PDP further includes a light shielding film (45), extending in bands along the display line direction, formed on the internal surface of the front substrate (11) to overlay each area S2 between the adjacent display lines L and extending between the display electrodes X and Y.
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公开(公告)号：DE69122722T2
公开(公告)日：1997-03-06
申请号：DE69122722
申请日：1991-11-27
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE
IPC: H04N5/66 , G09G3/20 , G09G3/28 , G09G3/288 , G09G3/291 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/297 , G09G3/298 , G09G3/30 , H04N5/70
Abstract: A driving circuit for a flat display panel formed of a plurality of cells arranged in lines and each having a memory function is adapted to produce a desired gradation of visual brightness in an image displayed on the display panel during a frame time period, the frame time period being divided into a series of subframes, and each subframe comprising an address period and a display period subsequent to the address period. The driving circuit comprises means for selecting pixels to be activated in respective subframes of the frame time period and means for activating the selected pixels during the address period of a subframe and for lighting the activated pixels in the display period of the respective subframe. The activating means is adapted to apply sustain pulses to all the pixels of the display during the display periods of the subframes and thereby illuminate activated pixels. The selecting means is adapted to select pixels for activation in subframes of a frame such that the cumulative number of sustain pulses applied to each pixel produces the desired gradation of brightness of the image displayed during the frame time period. The activation means is adapted to address selected pixels in the plurality of lines during an address period of a subframe, which is common to said plurality of lines.
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公开(公告)号：DE3586142D1
公开(公告)日：1992-07-09
申请号：DE3586142
申请日：1985-03-14
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE , NIINUMA ATUO
Abstract: An AC driving surface discharge display panel has a matrix arrangement of a plurality of display dots each of which comprises a pair of display cell and selection cell. Firstly, all display cells on a selected line are simultaneously fired, by applying a firing voltage between pairing parallel display electrodes defining said display cell line. Next, a discharge information stored unwanted display cell among said fired display cell line is selectively erased by discharging an adjacent pairing selection cell. An address sequence of the present invention comprising the line firing step and selective erasing step is performed with wide operation margin.
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公开(公告)号：DE3867252D1
公开(公告)日：1992-02-13
申请号：DE3867252
申请日：1988-02-16
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE , NANTO TOSHIYUKI
IPC: H01J11/14 , H01J11/24 , H01J11/26 , H01J11/28 , H01J11/36 , H01J11/38 , H01J11/42 , H01J11/50 , H01J17/20 , H01J17/49
Abstract: A fluorescent gas-discharge display panel, in which a fluorescent material (8) is excited by a gas discharge therein, contains a gas mixture of neon, argon and xenon as the discharge gas (9). Typically, the argon gas content is more than 5% by partial pressure, and the xenon gas less than 10%. The argon gas content contributes to produce a pure and high peak of green light spectrum and to reduce the orange light spectrum produced by the discharge of the neon gas. Other characteristics, such as operation voltages, brightness, luminous efficacy, and operation life, are kept satisfactory.
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公开(公告)号：DE3175921D1
公开(公告)日：1987-03-19
申请号：DE3175921
申请日：1981-11-17
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE , MIYASHITA YOSHINORI , SUGIMOTO YOSHIMI , SEI HIDEO , ANDOH SHIZUO
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Patent Agency Ranking
公开(公告)号：CA1063148A
公开(公告)日：1979-09-25
申请号：CA266051
申请日：1976-11-18
Applicant: FUJITSU LTD
Inventor： YAMASHITA HIDEO , ANDOH SHIZUO , SHINODA TSUTAE
Abstract: A gas discharge display panel which is an improvement over the type having electrodes arranged on a substrate and a dielectric layer insulating the electrodes from a gas-filled space is described. According to the invention, at least the surface portion of the dielectric layer which is in contact with the gas-filled space is made from a material which is a mixture of two or more Alkali-earth compounds. This is most easily done by providing over the usual dielectric layer an overcoat which may, for example, be composed of a mixture of CaO and SrO. The invention reduces considerably the firing and sustaining voltages.
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公开(公告)号：DE69621724D1
公开(公告)日：2002-07-18
申请号：DE69621724
申请日：1996-08-20
Applicant: FUJITSU LTD
Inventor： NANTO TOSHIYUKI , NAKAHARA HIROYUKI , AWAJI NORYUKI , WAKITANI MASAYUKI , SHINODA TSUTAE , KONNO KEIICHIRO , YANAGIBASHI YASUO , SAKAMOTO NAOHITO
IPC: H01J9/02 , H01J9/24 , H01J11/14 , H01J11/22 , H01J11/24 , H01J11/28 , H01J11/32 , H01J11/34 , H01J11/36 , H01J11/38 , H01J11/42 , H01J11/44 , H01J17/04 , H01J17/49
Abstract: A surface discharge type plasma display panel (PDP) includes a pair of front and rear substrates (11, 21) with a discharge space (30) therebetween and a plurality of pairs of display electrodes on internal surface of either the front or rear substrate. The display electrodes extend along each display line L. The PDP further includes a light shielding film (45), extending in bands along the display line direction, formed on the internal surface of the front substrate (11) to overlay each area S2 between the adjacent display lines L and extending between the display electrodes X and Y.
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公开(公告)号：DE69125508T2
公开(公告)日：1997-07-10
申请号：DE69125508
申请日：1991-11-27
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE
IPC: H04N5/66 , G09G3/20 , G09G3/28 , G09G3/288 , G09G3/291 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/297 , G09G3/298 , G09G3/30 , H04N5/70
Abstract: A driving circuit for a flat display panel formed of a plurality of cells arranged in lines and each having a memory function is adapted to produce a desired gradation of visual brightness in an image displayed on the display panel during a frame time period, the frame time period being divided into a series of subframes, and each subframe comprising an address period and a display period subsequent to the address period. The driving circuit comprises means for selecting pixels to be activated in respective subframes of the frame time period and means for activating the selected pixels during the address period of a subframe and for lighting the activated pixels in the display period of the respective subframe. The activating means is adapted to apply sustain pulses to all the pixels of the display during the display periods of the subframes and thereby illuminate activated pixels. The selecting means is adapted to select pixels for activation in subframes of a frame such that the cumulative number of sustain pulses applied to each pixel produces the desired gradation of brightness of the image displayed during the frame time period. The activation means is adapted to address selected pixels in the plurality of lines during an address period of a subframe, which is common to said plurality of lines.
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公开(公告)号：DE69125508D1
公开(公告)日：1997-05-07
申请号：DE69125508
申请日：1991-11-27
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE
IPC: H04N5/66 , G09G3/20 , G09G3/28 , G09G3/288 , G09G3/291 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/297 , G09G3/298 , G09G3/30 , H04N5/70
Abstract: A driving circuit for a flat display panel formed of a plurality of cells arranged in lines and each having a memory function is adapted to produce a desired gradation of visual brightness in an image displayed on the display panel during a frame time period, the frame time period being divided into a series of subframes, and each subframe comprising an address period and a display period subsequent to the address period. The driving circuit comprises means for selecting pixels to be activated in respective subframes of the frame time period and means for activating the selected pixels during the address period of a subframe and for lighting the activated pixels in the display period of the respective subframe. The activating means is adapted to apply sustain pulses to all the pixels of the display during the display periods of the subframes and thereby illuminate activated pixels. The selecting means is adapted to select pixels for activation in subframes of a frame such that the cumulative number of sustain pulses applied to each pixel produces the desired gradation of brightness of the image displayed during the frame time period. The activation means is adapted to address selected pixels in the plurality of lines during an address period of a subframe, which is common to said plurality of lines.
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公开(公告)号：DE69122722D1
公开(公告)日：1996-11-21
申请号：DE69122722
申请日：1991-11-27
Applicant: FUJITSU LTD
Inventor： SHINODA TSUTAE
IPC: H04N5/66 , G09G3/20 , G09G3/28 , G09G3/288 , G09G3/291 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/297 , G09G3/298 , G09G3/30 , H04N5/70
Abstract: A driving circuit for a flat display panel formed of a plurality of cells arranged in lines and each having a memory function is adapted to produce a desired gradation of visual brightness in an image displayed on the display panel during a frame time period, the frame time period being divided into a series of subframes, and each subframe comprising an address period and a display period subsequent to the address period. The driving circuit comprises means for selecting pixels to be activated in respective subframes of the frame time period and means for activating the selected pixels during the address period of a subframe and for lighting the activated pixels in the display period of the respective subframe. The activating means is adapted to apply sustain pulses to all the pixels of the display during the display periods of the subframes and thereby illuminate activated pixels. The selecting means is adapted to select pixels for activation in subframes of a frame such that the cumulative number of sustain pulses applied to each pixel produces the desired gradation of brightness of the image displayed during the frame time period. The activation means is adapted to address selected pixels in the plurality of lines during an address period of a subframe, which is common to said plurality of lines.
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