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公开(公告)号：DE102010047609B4
公开(公告)日：2017-03-16
申请号：DE102010047609
申请日：2010-10-07
Applicant: FUJITSU LTD , SOCIONEXT INC
Inventor： KOIDE MASATERU , MIZUTANI DAISUKE , INOUE AIICHIRO , YAMASHITA HIDEO , YAMAZAKI IWAO , KATO MASAYUKI , UENO SEIJI , IMAMURA KAZUYUKI
IPC: H01L23/50 , H01L25/065
Abstract: Multichipmodul mit: einer Basisplatte (10); einer Verdrahtungsplatte (20), die auf der Basisplatte (10) angeordnet ist und die eine Platte (22) und eine Verdrahtungsschicht (24), innerhalb der ein auf der Platte (22) angeordnetes Verdrahtungsmuster (26a) angeordnet ist, enthält; und einer Vielzahl von Chips (30A bis 30D), die auf der Verdrahtungsplatte (20) angeordnet sind, wobei jeder von der Vielzahl von Chips (30A bis 30D) mit wenigstens einem der anderen Chips (30A bis 30D) verbunden ist und die Vielzahl von Chips (30A bis 30D) und die Basisplatte (10) durch Durchgangslöcher (22a) elektrisch miteinander verbunden sind, die innerhalb der Verdrahtungsschicht (24) und der Platte (22) vorgesehen sind, wobei die Vielzahl der Chips vier Chips (30A bis 30D) enthält, die matrixartig angeordnet sind, und jeder der Chips (30A bis 30D) mit wenigstens einem der anderen Chips (30A bis 30D) über das Verdrahtungsmuster (26a) in einem Bereich verbunden ist, wo alle vier Chips (30A bis 30D) aneinandergrenzen, und wobei erste Pads mit einer ersten Dichte und zweite Pads mit einer zweiten Dichte, die niedriger als die erste Dichte ist, auf den unteren Flächen der Vielzahl von Chips (30A bis 30D) angeordnet sind, die ersten Pads mit dem Verdrahtungsmuster (26a) elektrisch verbunden sind und die zweiten Pads mit der Basisplatte (10) über die Durchgangslöcher (22a) elektrisch verbunden sind.
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公开(公告)号：DE69422003D1
公开(公告)日：2000-01-13
申请号：DE69422003
申请日：1994-08-26
Applicant: FUJITSU LTD
Inventor： YAMASHITA HIDEO , MATSUZAKI SHIGEHARU
Abstract: A command retry control apparatus, for use with an information processor which executes a program under pipeline control, translates an instruction contained in the program into commands in a processable form and executes the processing on a command basis. The command retry control apparatus determines (405), if an error occurs during the execution of the command, whether or not an operand value is a normal value and executes (408), when the operand value is the normal value, a command retry by stopping inputting a next command. The command retry control apparatus continues the processing by resuming (410, 411) the inputting of the next command when normally finishing the command retry. If the error reoccurs in the middle of the command retry, the command retry control apparatus decides (412) that the command is inexecutable and notifies (413) a management system of the occurrence of error. Such apparatus can enhance the applied range of a retry function in the pipeline control program of the information processor, thereby improving a reliability, an availability and a serviceability of the information processor.
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公开(公告)号：DE69409923T2
公开(公告)日：1998-08-20
申请号：DE69409923
申请日：1994-09-20
Applicant: FUJITSU LTD
Inventor： MATSUZAKI SHIGEHARU , YAMASHITA HIDEO
IPC: G06F11/14
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公开(公告)号：CA1063148A
公开(公告)日：1979-09-25
申请号：CA266051
申请日：1976-11-18
Applicant: FUJITSU LTD
Inventor： YAMASHITA HIDEO , ANDOH SHIZUO , SHINODA TSUTAE
Abstract: A gas discharge display panel which is an improvement over the type having electrodes arranged on a substrate and a dielectric layer insulating the electrodes from a gas-filled space is described. According to the invention, at least the surface portion of the dielectric layer which is in contact with the gas-filled space is made from a material which is a mixture of two or more Alkali-earth compounds. This is most easily done by providing over the usual dielectric layer an overcoat which may, for example, be composed of a mixture of CaO and SrO. The invention reduces considerably the firing and sustaining voltages.
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公开(公告)号：GB2383652B
公开(公告)日：2005-11-09
申请号：GB0206862
申请日：2002-03-22
Applicant: FUJITSU LTD
Inventor： OKAWA YASUKICHI , YAMASHITA HIDEO
Abstract: In the structure of register files composed of a master register file and a working register file, when data is read, the working register file is accessed. When data is written, the both the master register file and the working register file are accessed. In the working register file, data of the current window, and data preceded thereby, and data followed thereby are stored. Thus, even if the SAVE instruction or the RESTORE instruction are successively executed, instructions can be processed out of order. As a result, the efficiency of the process is improved.
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Patent Agency Ranking
公开(公告)号：DE69422003T2
公开(公告)日：2000-03-30
申请号：DE69422003
申请日：1994-08-26
Applicant: FUJITSU LTD
Inventor： YAMASHITA HIDEO , MATSUZAKI SHIGEHARU
Abstract: A command retry control apparatus, for use with an information processor which executes a program under pipeline control, translates an instruction contained in the program into commands in a processable form and executes the processing on a command basis. The command retry control apparatus determines (405), if an error occurs during the execution of the command, whether or not an operand value is a normal value and executes (408), when the operand value is the normal value, a command retry by stopping inputting a next command. The command retry control apparatus continues the processing by resuming (410, 411) the inputting of the next command when normally finishing the command retry. If the error reoccurs in the middle of the command retry, the command retry control apparatus decides (412) that the command is inexecutable and notifies (413) a management system of the occurrence of error. Such apparatus can enhance the applied range of a retry function in the pipeline control program of the information processor, thereby improving a reliability, an availability and a serviceability of the information processor.
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公开(公告)号：DE602006013079D1
公开(公告)日：2010-05-06
申请号：DE602006013079
申请日：2006-01-27
Applicant: FUJITSU LTD
Inventor： KAN RYUJI , YAMASHITA HIDEO , YOSHIDA TOSHIO
IPC: G06F9/30
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公开(公告)号：GB2383652A
公开(公告)日：2003-07-02
申请号：GB0206862
申请日：2002-03-22
Applicant: FUJITSU LTD
Inventor： OKAWA YASUKICHI , YAMASHITA HIDEO
Abstract: In a structure of register files composed of a master register file (MRF) and a working register file (WRF), when data is read, the working register file is accessed. When data is written, both the master register file (MRF) and the working register file are updated. The MRF holds data of all the register windows. In the working register file (WRF), data of the current window, of the window preceded thereby, and of the window followed thereby are stored. Thus, even if a SAVE instruction or a RESTORE instruction are successively executed, instructions can be processed out of order. As a result, the efficiency of the process is improved.
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公开(公告)号：DE69409923D1
公开(公告)日：1998-06-04
申请号：DE69409923
申请日：1994-09-20
Applicant: FUJITSU LTD
Inventor： MATSUZAKI SHIGEHARU , YAMASHITA HIDEO
IPC: G06F11/14
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公开(公告)号：DE102010047609A1
公开(公告)日：2011-04-28
申请号：DE102010047609
申请日：2010-10-07
Applicant: FUJITSU LTD , FUJITSU SEMICONDUCTOR LTD
Inventor： KOIDE MASATERU , MIZUTANI DAISUKE , INOUE AIICHIRO , YAMASHITA HIDEO , YAMAZAKI IWAO , KATO MASAYUKI , UENO SEIJI , IMAMURA KAZUYUKI
IPC: H01L23/50 , H01L25/065
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