公开(公告)号：EP2083424A1

公开(公告)日：2009-07-29

申请号：EP09156495.5

申请日：2000-09-27

Applicant: Fujitsu Microelectronics Limited

Inventor： Fujioka, Shinya ,  Kawakubo, Tomohiro ,  Nishimura, Koichi ,  Sato, Kotoku

IPC: G11C14/00

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/406 ,  G11C2207/2227

Abstract: A semiconductor memory device comprises an internal voltage generator (18) which, when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator (18) consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit (14) inactivates the internal voltage generator (18). When the internal voltage generator (18) is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. During the low power consumption mode, an external voltage supplying circuit supplies a power supply voltage supplied from the exterior as the internal voltage to a predetermined internal circuit. Even when the internal voltage generator (18) is inactivated, therefore, the power supply voltage is supplied to the power supply terminal of each internal circuit, which results in preventing a leak path.
For low power mode, data are saved from a dynamic memory to a flash memory. During low power mode, refresh operation of the dynamic memory is prohibited.

Abstract translation: 一种半导体存储器件包括内部电压发生器（18），该内部电压发生器在被激活时产生要提供给内部电路的内部电压。 操作内部电压发生器（18）消耗预定量的功率。 响应于来自外部的控制信号，入口电路（14）使内部电压发生器（18）不起作用。 当内部电压发生器（18）未激活时，不会产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 在低功耗模式期间，外部电压提供电路将从外部提供的电源电压作为内部电压提供给预定的内部电路。 因此，即使当内部电压发生器（18）未被激活时，电源电压也被提供给每个内部电路的电源端子，这导致防止泄漏路径。 对于低功耗模式，数据从动态存储器保存到闪存。 在低功耗模式下，动态存储器的刷新操作被禁止。

公开(公告)号：EP2056300A3

公开(公告)日：2009-06-17

申请号：EP09152393.6

申请日：2000-02-10

Applicant: Fujitsu Microelectronics Limited

Inventor： Mori, Kaoru ,  Kitamoto, Ayako ,  Matsumiya, Masato ,  Takita, Masato ,  Yamada, Shinichi ,  Nishimura, Koichi ,  Hatakeyama, Atsushi

IPC: G11C7/08 ,  G11C11/4091 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/065

Abstract: A transistor (11) of a driver (5) in a semiconductor integrated circuit has its gate connected to a controlling circuit (41), and has its drain connected to a sense amplifier (AMP). The controlling circuit (41)supplies the gate of the transistor (11) with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor (11) in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor (11). Accordingly, the amplifying speed of the sense amplifier (AMP) is heightened without altering the sense amplifier (AMP) and the driver (5). Besides, the amplifying speed of the sense amplifier (AMP) is heightened without raising the power supply voltage which supplies the carriers to the driver (5).

Abstract translation: 半导体集成电路中的驱动器（5）的晶体管（11）的栅极连接到控制电路（41），并且其漏极连接到读出放大器（AMP）。 控制电路（41）向晶体管（11）的栅极提供超过或低于其它电源电压的栅极 - 源极电压。 与在晶体管（11）的栅极和源极之间提供电源电压的情况相比，导通状态下的晶体管（11）的漏极 - 源极电阻变得足够低。 因此，读出放大器（AMP）的放大速度提高而不改变读出放大器（AMP）和驱动器（5）。 此外，增强读出放大器（AMP）的放大速度，而不会提供将载波提供给驱动器（5）的电源电压。

公开(公告)号：EP1100089B1

公开(公告)日：2009-05-27

申请号：EP00308482.9

申请日：2000-09-27

Applicant: Fujitsu Microelectronics Limited

Inventor： Fujioka, Shinya ,  Kawakubo, Tomohiro ,  Nishimura, Koichi ,  Sato, Kotoku

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/406 ,  G11C2207/2227

公开(公告)号：EP2053612A2

公开(公告)日：2009-04-29

申请号：EP09152398.5

申请日：2000-02-10

Applicant: Fujitsu Microelectronics Limited

Inventor： Mori, Kaoru ,  Kitamoto, Ayako ,  Matsumiya, Masato ,  Takita, Masato ,  Yamada Shinichi ,  Nishimura, Koichi ,  Hatakeyama, Atsushi

IPC: G11C7/08 ,  G11C11/4091 ,  G11C5/14

CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/065

Abstract: A transistor (11) of a driver (5) in a semiconductor integrated circuit has its gate connected to a controlling circuit (41), and has its drain connected to a sense amplifier (AMP). The controlling circuit (41) supplies the gate of the transistor (11) with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor (11) in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor (11). Accordingly, the amplifying speed of the sense amplifier (AMP) is heightened without altering the sense amplifier (AMP) and the driver (5). Besides, the amplifying speed of the sense amplifier (AMP) isheightened without raising the power supply voltage which supplies the carriers to the driver (5).

Abstract translation: 半导体集成电路中的驱动器（5）的晶体管（11）的栅极连接到控制电路（41），并且其漏极连接到读出放大器（AMP）。 控制电路（41）向晶体管（11）的栅极提供超过或低于其它电源电压的栅极 - 源极电压。 与在晶体管（11）的栅极和源极之间提供电源电压的情况相比，导通状态下的晶体管（11）的漏极 - 源极电阻变得足够低。 因此，读出放大器（AMP）的放大速度提高而不改变读出放大器（AMP）和驱动器（5）。 此外，读出放大器（AMP）的放大速度加快，而不会提供将载波提供给驱动器（5）的电源电压。

公开(公告)号：EP2053612A3

公开(公告)日：2009-06-24

申请号：EP09152398.5

申请日：2000-02-10

Applicant: Fujitsu Microelectronics Limited

Inventor： Mori, Kaoru ,  Kitamoto, Ayako ,  Matsumiya, Masato ,  Takita, Masato ,  Yamada Shinichi ,  Nishimura, Koichi ,  Hatakeyama, Atsushi

IPC: G11C7/08 ,  G11C11/4091 ,  G11C5/14

CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/065

Abstract: A transistor (11) of a driver (5) in a semiconductor integrated circuit has its gate connected to a controlling circuit (41), and has its drain connected to a sense amplifier (AMP). The controlling circuit (41) supplies the gate of the transistor (11) with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor (11) in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor (11). Accordingly, the amplifying speed of the sense amplifier (AMP) is heightened without altering the sense amplifier (AMP) and the driver (5). Besides, the amplifying speed of the sense amplifier (AMP) isheightened without raising the power supply voltage which supplies the carriers to the driver (5).

Abstract translation: 半导体集成电路中的驱动器（5）的晶体管（11）的栅极连接到控制电路（41），漏极连接到读出放大器（AMP）。 控制电路（41）向晶体管（11）的栅极提供超过或低于其他电源电压的栅极 - 源极电压。 与在晶体管（11）的栅极和源极之间提供电源电压的情况相比，晶体管（11）的导通状态下的漏极 - 源极电阻变得足够低。 因此，读出放大器（AMP）的放大速度被提高而不改变读出放大器（AMP）和驱动器（5）。 此外，在不提高向驱动器（5）供应载体的电源电压的情况下，读出放大器（AMP）的放大速度变高。

公开(公告)号：EP2056300A2

公开(公告)日：2009-05-06

申请号：EP09152393.6

申请日：2000-02-10

Applicant: Fujitsu Microelectronics Limited

Inventor： Mori, Kaoru ,  Kitamoto, Ayako ,  Matsumiya, Masato ,  Takita, Masato ,  Yamada, Shinichi ,  Nishimura, Koichi ,  Hatakeyama, Atsushi

IPC: G11C7/08 ,  G11C11/4091 ,  G11C5/14

CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/065

Abstract: A transistor (11) of a driver (5) in a semiconductor integrated circuit has its gate connected to a controlling circuit (41), and has its drain connected to a sense amplifier (AMP). The controlling circuit (41)supplies the gate of the transistor (11) with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor (11) in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor (11). Accordingly, the amplifying speed of the sense amplifier (AMP) is heightened without altering the sense amplifier (AMP) and the driver (5). Besides, the amplifying speed of the sense amplifier (AMP) is heightened without raising the power supply voltage which supplies the carriers to the driver (5).

Abstract translation: 半导体集成电路中的驱动器（5）的晶体管（11）的栅极连接到控制电路（41），漏极连接到读出放大器（AMP）。 控制电路（41）向晶体管（11）的栅极提供超过或低于其他电源电压的栅极 - 源极电压。 与在晶体管（11）的栅极和源极之间提供电源电压的情况相比，晶体管（11）的导通状态下的漏极 - 源极电阻变得足够低。 因此，读出放大器（AMP）的放大速度被提高而不改变读出放大器（AMP）和驱动器（5）。 此外，读出放大器（AMP）的放大速度升高而不提高向驱动器（5）供应载体的电源电压。

公开(公告)号：EP2083423A1

公开(公告)日：2009-07-29

申请号：EP09156492.2

申请日：2000-09-27

Applicant: Fujitsu Microelectronics Limited

Inventor： Fujioka, Shinya ,  Kawakubo, Tomohiro ,  Nishimura, Koichi ,  Sato, Kotoku

IPC: G11C11/406

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/406 ,  G11C2207/2227

Abstract: A semiconductor memory device comprises an internal voltage generator (18) which, when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator (18) consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit (14) inactivates the internal voltage generator (18). When the internal voltage generator (18) is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. During the low power consumption mode, an external voltage supplying circuit supplies a power supply voltage supplied from the exterior as the internal voltage to a predetermined internal circuit. Even when the internal voltage generator (18) is inactivated, therefore, the power supply voltage is supplied to the power supply terminal of each internal circuit, which results in preventing a leak path.
During low power consumption mode, refresh of the dynamic memory cells is prohibited.

Abstract translation: 半导体存储器件包括内部电压发生器（18），其在被激活时产生将被提供给内部电路的内部电压。 操作内部电压发生器（18）消耗预定量的功率。 响应于来自外部的控制信号，入口电路（14）使内部电压发生器（18）失活。 当内部电压发生器（18）失活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 在低功耗模式期间，外部电压供给电路将从外部供给的电源电压作为内部电压供给到规定的内部电路。 因此，即使当内部电压发生器（18）失活时，电源电压被提供给每个内部电路的电源端子，这导致防止泄漏路径。 在低功耗模式下，禁止刷新动态存储单元。