公开(公告)号：EP2503390A3

公开(公告)日：2013-01-09

申请号：EP12173143.4

申请日：2003-02-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  G03F1/32 ,  H01L23/58 ,  H01L21/768

Abstract: A phase shift mask, comprising a phase shifter film (302) formed on a transparent substrate (300), and a light shield film (314) formed in a scribe line region (312) on said transparent substrate (300). A region surrounded by said scribe line region (312) is constituted of an integrated circuit region (304) with which an integrated circuit part is to be formed and a peripheral edge region (306) with which a peripheral edge part in a periphery of said integrated circuit part is to be formed. The light shield film (314) is further formed at least in a part of said peripheral edge region (306) and said integrated circuit region (304).

公开(公告)号：EP2706410A1

公开(公告)日：2014-03-12

申请号：EP13195857.1

申请日：2003-02-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  H01L23/00 ,  H01L23/58 ,  H01L21/768

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device, comprising: a substrate which includes a first edge region, an integrated circuit region surrounded by the first edge region in a plan view and a second edge region located between the first edge region and the integrated circuit region in a plan view; a first interlayer insulation film (116) formed above the substrate; a contact hole formed in the first interlayer insulation film of the integrated circuit region; a first trench (131) formed in the first interlayer insulation film of the first edge region; a second trench (131), which is connected to the first trench at two positions, formed in the first interlayer insulation film of the second edge region; a second interlayer insulation film (117) formed above the first interlayer insulation film; a third trench (132), which is wider than the first trench in a plan view and which is connected to the first trench, formed in the second interlayer insulation film of the first region; a fourth trench (132), which is wider than the second trench in a plan view, which is connected to the third trench at two position in a plan view and which is connected to the second trench, formed in the second interlayer insulation film of the second region; a fifth trench formed in the second interlayer insulation film of the integrated circuit region; and a first metal film (120a) formed in the contact hole, the first trench, the second trench, the third trench, the fourth trench and the fifth trench, the first edge region includes a main-wall part (2) which includes the first trench and the third trench, and the second edge region includes a first sub-wall part (3b) which includes the second trench and the fourth trench.

Abstract translation: 一种半导体器件，包括：在平面图中包括第一边缘区域，被所述第一边缘区域包围的集成电路区域和位于所述第一边缘区域和所述集成电路区域之间的第二边缘区域的基板; 形成在所述基板上方的第一层间绝缘膜（116） 形成在集成电路区域的第一层间绝缘膜中的接触孔; 形成在所述第一边缘区域的所述第一层间绝缘膜中的第一沟槽（131） 第二沟槽（131），其形成在所述第二边缘区域的所述第一层间绝缘膜中的两个位置处连接到所述第一沟槽; 形成在所述第一层间绝缘膜之上的第二层间绝缘膜; 第三沟槽（132），其在平面图中比所述第一沟槽宽，并且连接到所述第一沟槽，形成在所述第一区域的所述第二层间绝缘膜中; 在平面图中比第二沟槽宽的第四沟槽（132），其在平面图的两个位置处连接到第三沟槽，并且连接到形成在第二沟槽中的第二层间绝缘膜中 第二区; 形成在所述集成电路区域的第二层间绝缘膜中的第五沟槽; 以及形成在所述接触孔，所述第一沟槽，所述第二沟槽，所述第三沟槽，所述第四沟槽和所述第五沟槽中的第一金属膜（120a），所述第一边缘区域包括主壁部分（2） 第一沟槽和第三沟槽，并且第二边缘区域包括包括第二沟槽和第四沟槽的第一子壁部分（3b）。

公开(公告)号：EP2503390A2

公开(公告)日：2012-09-26

申请号：EP12173143.4

申请日：2003-02-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  G03F1/32 ,  H01L23/58 ,  H01L21/768

Abstract: A phase shift mask, comprising a phase shifter film (302) formed on a transparent substrate (300), and a light shield film (314) formed in a scribe line region (312) on said transparent substrate (300). A region surrounded by said scribe line region (312) is constituted of an integrated circuit region (304) with which an integrated circuit part is to be formed and a peripheral edge region (306) with which a peripheral edge part in a periphery of said integrated circuit part is to be formed. The light shield film (314) is further formed at least in a part of said peripheral edge region (306) and said integrated circuit region (304).

Abstract translation: 一种相移掩模，包括形成在透明基板（300）上的移相膜（302）和形成在所述透明基板（300）上的划线区域（312）中的遮光膜（314）。 由所述划线区域（312）围绕的区域由要形成集成电路部分的集成电路区域（304）和周边边缘区域（306）构成，周边区域 集成电路部分要形成。 至少在所述周缘区域（306）和集成电路区域（304）的至少一部分中进一步形成遮光膜（314）。