公开(公告)号：JPH03114383A

公开(公告)日：1991-05-15

申请号：JP25313889

申请日：1989-09-28

Applicant: GRAPHICS COMMUNICATION TECH ,  BELL COMMUNICATIONS RES

Inventor： MARUYAMA MASANORI ,  FUJIWARA HIROSHI ,  JOFU HIROO ,  IWASAKI ISAO ,  MINGUUTEINGU SAN

Abstract: PURPOSE: To provide a signal conversion device, suitable for efficient digital transmission by arbitrarily selecting the scan mode of an input signal. CONSTITUTION: When an inputted signal is subjected to an orthogonal conversion and is outputted, data obtained by orthogonal conversion is stored in a second data storage part 15, and address information of a sequence corresponding to the desired scan mode is given to this data storage part 15 to read and output the data stored. When the inputted signal is subjected to inverse orthogonal conversion and is outputted, the input signal to be subjected to inverse orthogonal conversion is stored in a first data storage part 12 and a read out. In this case, address information of a sequence corresponding to a desired scan mode is given to the data storage part 12 to store or read out the data, and this data is subjected to an inverse orthogonal conversion and is outputted. Thus efficient digital transmission is executed.

公开(公告)号：JPH0636592B2

公开(公告)日：1994-05-11

申请号：JP25313889

申请日：1989-09-28

Applicant: GRAPHICS COMMUNICATION TECH ,  BELL COMMUNICATIONS RES

Inventor： MARUYAMA MASANORI ,  FUJIWARA HIROSHI ,  JOFU HIROO ,  IWASAKI ISAO ,  MINGUUTEINGU SAN

IPC: H04N7/133

公开(公告)号：JPH0417063A

公开(公告)日：1992-01-21

申请号：JP11878690

申请日：1990-05-10

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  IWASAKI ISAO ,  FUJIWARA HIROSHI ,  MIN TEIN SAN

IPC: G06F7/38 ,  G06F17/10

Abstract: PURPOSE:To add an arbitrary set value to accumulating calculation to give a width to an accumulated content and make rounding calculation by providing an adder, register, selecting means, etc. CONSTITUTION:An adder 100 takes the sum of two inputs of an original data input 10 and another input 40 to each other and a register 200 latches the calculated result of the adder 100. A selector 300 inputs the latched output of the register 200 through a feedback loop 30 and selects and outputs the latched output to the adder 100 as the another input 40. Therefore, an arbitrary set value can be added to the accumulating calculation and an initial value can be added for rounding calculation, since either the latched output of the register 220 or an arbitrary set value can be selected freely as the another input 40 to the adder 100.

公开(公告)号：JPH03268592A

公开(公告)日：1991-11-29

申请号：JP6768390

申请日：1990-03-17

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  IWASAKI ISAO ,  JOFU HIROO ,  FUJIWARA HIROSHI

IPC: G06T9/00 ,  H04N1/41 ,  H04N7/00 ,  H04N19/60

Abstract: PURPOSE:To attain the individual test of a device inside in addition to the execution of a signal conversion function without forming a new signal line by connecting respective connection switching parts to respective I/O part of an image signal converter and a DC-AC conversion/reversed DC-AC conversion part and attaining connection states appropriate for a test specified from the external. CONSTITUTION:An external control signal inputted through a signal line 301 is respectively applied to a connection switching part S1, respective DC-AC conversion/reversed DC-AC conversion parts 101, 103, and a connection switching part S9. At the time of inputting a mode setting signal for setting up a circuit operation mode through a signal line 201 when the external control signal specifies a DC-AC conversion mode, the connecting switching part S1 to which DC-AC conversion is instructed applies the instruction to a mode selection part 104 through a signal line 211 and the mode selection part 104 applies a switching signal for switching the connection of signals to respective connection switching parts S3 to S6 through a signal line 302. When the external control signal specifies a reversed DC-AC conversion mode, a signal line 210B is connected to a signal line 212 by the connection switching part S9 and the signal line 210B is used for inputting the mode setting signal.

公开(公告)号：JPH0416066A

公开(公告)日：1992-01-21

申请号：JP11878490

申请日：1990-05-10

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  IWASAKI ISAO ,  FUJIWARA HIROSHI ,  MIN TEIN SAN

IPC: H04N19/60 ,  H04N1/41 ,  H04N11/02 ,  H04N19/42 ,  H04N19/423 ,  H04N19/625 ,  H04N19/85

Abstract: PURPOSE:To execute the calculation with high accuracy by setting a transformation coefficient of a DC term to be a 2's power so as to eliminate the deterioration in the calculation accuracy attended with a ROM table of a definite bit width. CONSTITUTION:A linear discrete cosine transformation(DCT) section 100 receives m-set of inputs 10 to apply linear DCT transformation. An intermediate RAM 300 latches the result of conversion and a 2-dimension DCT section 200 applies 2-dimension transformation to a value after linear transformation as an object. A scaling device 400 applies scaling to the result of the 2-dimension transformation. The DCT sections 100, 200 multiplies a transformation coefficient as N=2 to set the transformation coefficient of a DC term to D=0.5. The scaling of a multiple of 1/2 means one bit shift and it is very simple, a value of 2 or below is rounded at an output 40 and high-order 12bits from a bit of 2 are used as a final output 50.

公开(公告)号：JPH0417464A

公开(公告)日：1992-01-22

申请号：JP11973390

申请日：1990-05-11

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  IWASAKI ISAO ,  FUJIWARA HIROSHI ,  MIN TEIN SAN

IPC: H04N19/60 ,  G06T9/00 ,  H03M7/30 ,  H04N1/41 ,  H04N1/415 ,  H04N11/04 ,  H04N19/42 ,  H04N19/423 ,  H04N19/426 ,  H04N19/625

Abstract: PURPOSE:To make the device small and to reduce the power consumption by using an arithmetic ROM in common for forward and reverse transformation. CONSTITUTION:Let eight inputs be (a)-(h), then ROM 501, 505 receiving two inputs (a), (b) output a prescribed arithmetic result. Similarly, ROM 502, 506, 509, 512 receives inputs (c), (d) and output processing arithmetic result, ROM 503, 507, 510, 513 receives inputs (e), (f) and output processing arithmetic result, and ROM 504, 508 511, 514 receives inputs (g), (h) and output processing arithmetic result respectively. Moreover, outputs of the ROM 503 and the ROM 504, the ROM 507 and the ROM 508, the ROM 510 and the ROM 511, and the ROM 513 and the ROM 514 are added respectively by adders 601-602. Ten outputs 80 are outputted by IDCT arithmetic operation and eight bypass outputs 81 are outputted as DCT arithmetic processing.

公开(公告)号：JPH0417026A

公开(公告)日：1992-01-21

申请号：JP11878590

申请日：1990-05-10

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  IWASAKI ISAO ,  FUJIWARA HIROSHI ,  MIN TEIN SAN

IPC: G06F7/38

Abstract: PURPOSE:To decide an overflow and to make high speed clipping available with simple circuit configuration by comparing code bits before and after an arithmetic operation with each other. CONSTITUTION:An arithmetic means 300 which inputs input data including code bits and a first means 100 which compares a code bit obtained from the calculated result of the arithmetic means 300 with the code bit of the input data and discriminates the occurrence of a positive or negative overflow are provided. In addition, a second means 200 which clips the calculated result to the positive maximum value when the occurrence of an positive overflow is discriminated and to the negative minimum value when the occurrence of an negative overflow is discriminated. Therefore, high-speed clipping can be realized with simple comparison.