公开(公告)号：JPH03114383A

公开(公告)日：1991-05-15

申请号：JP25313889

申请日：1989-09-28

Applicant: GRAPHICS COMMUNICATION TECH ,  BELL COMMUNICATIONS RES

Inventor： MARUYAMA MASANORI ,  FUJIWARA HIROSHI ,  JOFU HIROO ,  IWASAKI ISAO ,  MINGUUTEINGU SAN

Abstract: PURPOSE: To provide a signal conversion device, suitable for efficient digital transmission by arbitrarily selecting the scan mode of an input signal. CONSTITUTION: When an inputted signal is subjected to an orthogonal conversion and is outputted, data obtained by orthogonal conversion is stored in a second data storage part 15, and address information of a sequence corresponding to the desired scan mode is given to this data storage part 15 to read and output the data stored. When the inputted signal is subjected to inverse orthogonal conversion and is outputted, the input signal to be subjected to inverse orthogonal conversion is stored in a first data storage part 12 and a read out. In this case, address information of a sequence corresponding to a desired scan mode is given to the data storage part 12 to store or read out the data, and this data is subjected to an inverse orthogonal conversion and is outputted. Thus efficient digital transmission is executed.

公开(公告)号：JPH0636592B2

公开(公告)日：1994-05-11

申请号：JP25313889

申请日：1989-09-28

Applicant: GRAPHICS COMMUNICATION TECH ,  BELL COMMUNICATIONS RES

Inventor： MARUYAMA MASANORI ,  FUJIWARA HIROSHI ,  JOFU HIROO ,  IWASAKI ISAO ,  MINGUUTEINGU SAN

IPC: H04N7/133

公开(公告)号：JPH03106283A

公开(公告)日：1991-05-02

申请号：JP24445489

申请日：1989-09-20

Applicant: GRAPHICS COMMUNICATION TECH ,  BELL COMMUNICATIONS RES

Inventor： FUJIWARA HIROSHI ,  MARUYAMA MASANORI ,  JOFU HIROO ,  MIN TEIN SAN ,  KUN MIN YAN

IPC: F02B39/00 ,  G06T7/20 ,  G06T9/00 ,  G06T13/00 ,  G06T13/80 ,  H04M3/56 ,  H04N11/04

Abstract: PURPOSE: To efficiently execute the parallel process of an accurate dynamic vector by plural arithmetic means and to search the vector realtime by providing the dynamic vector detecting device with plural registers, plural arithmetic means for computing evaluation data and a dynamic vector data detecting means. CONSTITUTION: Device, (p-1) of registers 61 , 62 input respective pixel data in a 1st block successively from the initial stage to the succeeding stage and delay the data by prescribed time, and p arithmetic means 71 to 73 input respective pixel data in the 1st block or an output from any one of (p-1) registers 61 , 62 and respective pixel data in an intermediate block and operate evaluation data. The dynamic vector detecting means 18 seeks a minimum value and a position which are dynamic vector data by the use of p number of evaluation data, outputted from the p arithmetic means 71 to 73 . Consequently, an accurate dynamic vector is detected, and the parallel processing of the dynamic vector is executed efficiently by plural arithmetic means 71 to 73 .

公开(公告)号：JPH04340884A

公开(公告)日：1992-11-27

申请号：JP14080991

申请日：1991-05-16

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： KAKII EIJI ,  MARUYAMA MASANORI ,  FUJIWARA HIROSHI

IPC: H04N7/24 ,  H04N11/04 ,  H04N19/00

Abstract: PURPOSE:To prevent the degradation of the picture quality by directly transmitting the frame data for the code processing without suppressing the frame data when the frame skip is above the normal value. CONSTITUTION:A frame skip calculation part 21 counts the number of the frame synchronizing signal existing between the frame start signal and the next frame start signal. In this case, the sizes of the set value and the skip counted value are compared in a comparison part 22. When the skip counted value is below the set value, a switch 20 is brought down to the side of the solid line by the output of the comparison part 22. By this, the input data is inputted in a difference part 10. When the skip counted value is above the set value, the switch 20 is brought down to the side of the dotted line by the output of the comparison part 22. Thus, the input data is directly inputted into an encoding part 15 and is directly inputted in a frame memory 21.

公开(公告)号：JPH04330886A

公开(公告)日：1992-11-18

申请号：JP13050891

申请日：1991-05-02

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  FUJIWARA HIROSHI

IPC: H04B14/00 ,  H04N1/21 ,  H04N1/41 ,  H04N19/00 ,  H04N19/132 ,  H04N19/142 ,  H04N19/149 ,  H04N19/15 ,  H04N19/176 ,  H04N19/423 ,  H04N19/46 ,  H04N19/60 ,  H04N19/70 ,  H04N19/91

Abstract: PURPOSE:To prevent the occurrence of a logical overflowing at a transmitting buffer by performing the encoding only to a low frequency area when the storing quantity of the transmitting buffer is the logical buffer size or above at the time of the scene change. CONSTITUTION:A zigzag converting part 1 zigzag-converts the time arrangement sequence of an image signal, a quantizing part 2 quantizes the converted result, a variable length coding part 4 variable-length-codes in accordance with quantizing data and temporarily stores to a transmitting buffer 7. Further, a multiplexer 3 is provided between the quantizing part 2 and the variable length encoding part 4 and the selection is performed by a scene change discriminating part 5 and a logical overflowing discriminating part 6. That is, the scene change discriminating part 5 discriminates whether or not the scene change exists, the logical overflowing discriminating part 6 fetches the storing quantity of the transmitting buffer 7 and the discriminated result of the scene change discriminating part 5, and when the overflowing can be forecast, the encoding prohibiting data are selected and when the danger of the overflowing occurrence does not exist, the quantizing data are selected.

公开(公告)号：JPH03106282A

公开(公告)日：1991-05-02

申请号：JP24445689

申请日：1989-09-20

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： FUJIWARA HIROSHI ,  MARUYAMA MASANORI ,  JOFU HIROO

IPC: G06Q10/06 ,  G06T9/00 ,  G06T13/00 ,  G06T13/80 ,  H04N11/04

Abstract: PURPOSE:To detect an accurate dynamic vector and to expand a retrieving block when necessary by allowing operation modules to execute respective operations in parallel while utilizing picture element data or operated result data to be mutually used by the modules. CONSTITUTION:The dynamic vector detector is provided with (p) computing means 151 to 15p for computing evaluation data, (p) multi-connected registers 141 to 14p for delaying respective picture element data in the 1st block by a prescribed time and a dynamic vector data detecting means 16 for finding out the minimum value and a position. Then (m) multi-connected operation modules 4 each of which computes the minimum value and a position in a part of each of two areas adjacent to the 2nd block out of (m+1) divided blocks so that the output of the final register 14p in the preceding operation module is successively inputted to the succeeding operation module 4 to set up the number of picture elements, the number (m) of modules and the number (p) of arithmetic means under a prescribed condition. Consequently, an accurate dynamic vector can be detected and the retrieving blocks can be optionally expanded only by cascading plural operation modules 4 having the same constitution.

公开(公告)号：JPH02166917A

公开(公告)日：1990-06-27

申请号：JP32274488

申请日：1988-12-21

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： KINOSHITA TAIZO ,  MARUYAMA MASANORI

IPC: H03K21/16 ,  H03K23/00

Abstract: PURPOSE:To extract and output only a carry-out signal at the time of counting a terminal with a few hardware by utilizing the carry-out signal of a counter as it is. CONSTITUTION:The carry-out signal CO of the counter 1 is inputted to the clock terminal CK of a flip-flop 31 in a carry-out signal generation circuit 3. Also, a preset signal P is inputted to the reset terminal R of the flip-flop, and the output terminal Q is connected to the carry-in signal terminal C1 of the counter 1. The output Q of the flip-flop 31 is inputted to the input terminal on one side of an AND gate 33, and also, its inversion output is inputted to the input terminal on the other side of the AND gate 33 via a latch circuit 32, and the carry-out signal CO is extracted from the AND gate 33, then, a signal COB is outputted as a requested timing pulse. In such a manner, it is possible to output only the carry-out signal at the time of counting the terminal with a few hardware.

公开(公告)号：JPH0522710A

公开(公告)日：1993-01-29

申请号：JP3200291

申请日：1991-01-31

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： FUJIWARA HIROSHI ,  JOFU HIROO ,  MARUYAMA MASANORI ,  KAKII EIJI

IPC: G06T9/00 ,  H04N11/04 ,  H04N19/126 ,  H04N19/132 ,  H04N19/15 ,  H04N19/172 ,  H04N19/176 ,  H04N19/196 ,  H04N19/423 ,  H04N19/46 ,  H04N19/503 ,  H04N19/51 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/85 ,  H04N19/91

Abstract: PURPOSE:To reduce the deterioration of picture quality and also to select respective kinds of control from an external part by executing control in such a way that frame rate control is appropriately related with quantization step size control. CONSTITUTION:An orthogonal transformation part 130 makes the screen of one frame into blocks, respectively executes orthogonal transformation, permits them to be quantized(140) and makes them into variable length codes(150) so as to transmit them with a transmission buffer memory 170. A step size control part 600 decides the width of a discrete level in the quantization part 140. Next, minimum and maximum frame skip number set points Smin and Smix, a buffer normal value BL and a frame clock signal FST are inputted to a frame rate control part 700 and, moreover, motion information 3, buffer storage quantity B, an encoding frame start signal 9, encoding block cycle signal 10 and a step size Q are inputted as inner part signals. An encoding frame starting signal 5 is generated by a specified method based on the inputs so that a whole device selects the picture frame to be processed and controls it.

公开(公告)号：JPH04179384A

公开(公告)日：1992-06-26

申请号：JP30614890

申请日：1990-11-14

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  ICHIKAWA MASAHIRO

IPC: G06T9/00 ,  H04N1/41

Abstract: PURPOSE:To operate the efficient digital transmission of a picture signal by providing a means which designates a scan direction from the outside in order to designate the substaintial direction of a zigzag scan from the outside. CONSTITUTION:When an orthogonal transformation mode is designated, digital picture data 50 are transmitted to an orthogonal transforming/inverse orthogonal transforming part 13, and orthogonally transformed. And also, when an anti- orthogonal transformation mode is designated, the data are transmitted through a data storage part 12 to the orthogonal transforming/inverse orthogonal transforming part 13, and anti-orthogonally transformed. Then, for example, when the orthogonal transformation mode is designated, the storage and reading of a processed result 53 in and from a data storage part 15 are controlled by an address signal 57 from an address information generating part 17, and a horizontal scan and a vertical scan can be designated as a standard scan by a scan direction designation signal 70. Thus, the efficient digital transmission of the picture data can be operated.

公开(公告)号：JPH0417464A

公开(公告)日：1992-01-22

申请号：JP11973390

申请日：1990-05-11

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： MARUYAMA MASANORI ,  IWASAKI ISAO ,  FUJIWARA HIROSHI ,  MIN TEIN SAN

IPC: H04N19/60 ,  G06T9/00 ,  H03M7/30 ,  H04N1/41 ,  H04N1/415 ,  H04N11/04 ,  H04N19/42 ,  H04N19/423 ,  H04N19/426 ,  H04N19/625

Abstract: PURPOSE:To make the device small and to reduce the power consumption by using an arithmetic ROM in common for forward and reverse transformation. CONSTITUTION:Let eight inputs be (a)-(h), then ROM 501, 505 receiving two inputs (a), (b) output a prescribed arithmetic result. Similarly, ROM 502, 506, 509, 512 receives inputs (c), (d) and output processing arithmetic result, ROM 503, 507, 510, 513 receives inputs (e), (f) and output processing arithmetic result, and ROM 504, 508 511, 514 receives inputs (g), (h) and output processing arithmetic result respectively. Moreover, outputs of the ROM 503 and the ROM 504, the ROM 507 and the ROM 508, the ROM 510 and the ROM 511, and the ROM 513 and the ROM 514 are added respectively by adders 601-602. Ten outputs 80 are outputted by IDCT arithmetic operation and eight bypass outputs 81 are outputted as DCT arithmetic processing.