公开(公告)号：JPH03106283A

公开(公告)日：1991-05-02

申请号：JP24445489

申请日：1989-09-20

Applicant: GRAPHICS COMMUNICATION TECH ,  BELL COMMUNICATIONS RES

Inventor： FUJIWARA HIROSHI ,  MARUYAMA MASANORI ,  JOFU HIROO ,  MIN TEIN SAN ,  KUN MIN YAN

IPC: F02B39/00 ,  G06T7/20 ,  G06T9/00 ,  G06T13/00 ,  G06T13/80 ,  H04M3/56 ,  H04N11/04

Abstract: PURPOSE: To efficiently execute the parallel process of an accurate dynamic vector by plural arithmetic means and to search the vector realtime by providing the dynamic vector detecting device with plural registers, plural arithmetic means for computing evaluation data and a dynamic vector data detecting means. CONSTITUTION: Device, (p-1) of registers 61 , 62 input respective pixel data in a 1st block successively from the initial stage to the succeeding stage and delay the data by prescribed time, and p arithmetic means 71 to 73 input respective pixel data in the 1st block or an output from any one of (p-1) registers 61 , 62 and respective pixel data in an intermediate block and operate evaluation data. The dynamic vector detecting means 18 seeks a minimum value and a position which are dynamic vector data by the use of p number of evaluation data, outputted from the p arithmetic means 71 to 73 . Consequently, an accurate dynamic vector is detected, and the parallel processing of the dynamic vector is executed efficiently by plural arithmetic means 71 to 73 .

公开(公告)号：JPH03274920A

公开(公告)日：1991-12-05

申请号：JP7349390

申请日：1990-03-26

Applicant: GRAPHICS COMMUNICATION TECH

Inventor： FUJIWARA HIROSHI ,  SAKAGUCHI TOSHIBUMI ,  SHIMAZU AKIO ,  KUN MIN YAN ,  MIN TEIN SAN ,  KOU FUU TSUOU

IPC: H03M7/40 ,  H03M7/42

Abstract: PURPOSE:To accelerate the variable length encoding and decoding processing of input data by selecting variable length code word length data and variable length encoding data corresponding to the encoding rule of fixed length encoding input data executing the variable length encoding processing or the like. CONSTITUTION:In the fixed length encoding input data to be successively inputted, the data not knowing the encoding rule is outputted as the fixed length encoding data as it is, and the data knowing the encoding rule is successively outputted through an input data register 23 of a signal encoding part 4 for each bit. Then, plural variable length code word length tables 25 are refereed to and based on a select signal corresponding to the rule, a select circuit 30 selects the word length data corresponding to the rule from an encoding control unit 24. Similarly, a select circuit 31 selects the encoding data and the encoded variable length encoding data is outputted according to the rule from a transmitting data generating circuit 32. Then, the variable length encoding data is similarly decoded as well and therefore, without complicating configuration, the variable length data can be encoded and decoded at high speed.