公开(公告)号：EP4535414A1

公开(公告)日：2025-04-09

申请号：EP24168619.5

申请日：2024-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jain, Navneet K. ,  Kim, Juhan ,  Rashed, Mahbub

IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092

Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

公开(公告)号：EP4418320A1

公开(公告)日：2024-08-21

申请号：EP23191650.3

申请日：2023-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pritchard, David Charles ,  Mazza, James P. ,  Jain, Navneet K. ,  Yu, Hong

IPC: H01L27/02 ,  H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2027/1186620130101 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823871 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092

Abstract: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.

公开(公告)号：EP4398299A1

公开(公告)日：2024-07-10

申请号：EP23195592.3

申请日：2023-09-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mazza, James P. ,  Zeng, Jia ,  Zhu, Xuelian ,  Jain, Navneet K. ,  Rashed, Mahbub ,  Mazza, Jacob

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L2027/1187520130101 ,  G06F30/392 ,  H01L2027/1188120130101

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.