公开(公告)号：WO2016175793A1

公开(公告)日：2016-11-03

申请号：PCT/US2015/028256

申请日：2015-04-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： BACCHUS, Reza M. ,  POPE, Eric L. ,  LOH, Sze Hau

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F13/16 ,  G06F13/1694 ,  Y02D10/14

Abstract: A memory device includes a storage array, a first differential interface coupled to the storage array and including a first bidirectional signal channel to facilitate communication with an upstream device, and a second differential interface coupled to the first differential interface and including a second bidirectional signal channel to facilitate communication with a downstream device.

Abstract translation: 存储器件包括存储阵列，耦合到存储阵列的第一差分接口，并且包括第一双向信号通道以促进与上游设备的通信，以及耦合到第一差分接口的第二差分接口，并且包括第二双向信号通道 以便于与下游设备的通信。

公开(公告)号：WO2016175852A1

公开(公告)日：2016-11-03

申请号：PCT/US2015/028610

申请日：2015-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： BACCHUS, Reza M.

IPC: G06F11/16 ,  G11C29/44

CPC classification number: G11C29/44 ,  G11C5/04 ,  G11C29/42 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: In some examples, a memory module includes an error status indicator, an error address register, and error tracking circuitry. The error tracking circuitry may detect that memory data stored at a memory address for the memory module includes an error. In response, and without overwriting the memory data stored at the memory address, the error tracking circuitry may set the error status indicator and store the memory address in the error address register.

Abstract translation: 在一些示例中，存储器模块包括错误状态指示符，错误地址寄存器和错误跟踪电路。 错误跟踪电路可以检测存储在存储器模块的存储器地址处的存储器数据包括错误。 作为响应，并且不覆盖存储在存储器地址处的存储器数据，错误跟踪电路可以设置错误状态指示符并将存储器地址存储在错误地址寄存器中。

公开(公告)号：WO2017074292A1

公开(公告)日：2017-05-04

申请号：PCT/US2015/057268

申请日：2015-10-25

Applicant: HEWLETT-PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： BACCHUS, Reza M. ,  BENEDICT, Melvin K. ,  POPE, Eric L.

IPC: G11C11/401 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Abstract translation: 易失性存储器件包括易失性电荷存储单元的存储器阵列，用于跟踪自易失性存储器件接收到读取/写入命令以来的时间的计数器以及用于自动改变易失性存储器的控制元件 设备根据计数器跟踪的时间降低到低功耗状态。

公开(公告)号：WO2017065802A1

公开(公告)日：2017-04-20

申请号：PCT/US2015/055976

申请日：2015-10-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： BACCHUS, Reza M. ,  BENEDICT, Melvin K. ,  POPE, Eric L.

IPC: G11C11/406 ,  G06F11/10

CPC classification number: G06F11/106 ,  G11C7/04 ,  G11C11/4076

Abstract: A memory device includes storage locations to store data, and an internal controller to perform scrubbing of a portion of the data stored by at least one storage location of the storage locations. The memory device also includes an interface to communicate non-deterministically over a communication bus with a memory controller.

Abstract translation: 存储器设备包括存储位置以存储数据，以及内部控制器执行对存储位置的至少一个存储位置存储的数据的一部分的擦除。 存储设备还包括通过通信总线与存储控制器进行非确定性通信的接口。