公开(公告)号：WO2017155551A1

公开(公告)日：2017-09-14

申请号：PCT/US2016/022182

申请日：2016-03-11

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： KELLY, Terence P ,  MORREY, Charles B ,  CHAKRABARTI, Dhruva ,  KOLLI, Aasheesh ,  CAI, Qiong ,  WALTON, Andrew C ,  IZRAELEVITZ, Joseph

IPC: G06F12/16 ,  G06F9/312 ,  G06F9/30 ,  G06F11/30

Abstract: Examples herein involve storing registers in the event of a system failure. In examples herein, an association is made between a register and a location in persistent memory based on an execution of a process. Upon detection of the failure, the content of the register is stored to the persistent memory location based on the association.

Abstract translation: 这里的例子涉及在系统故障的情况下存储寄存器。 在这里的例子中，基于过程的执行，在寄存器和永久存储器中的位置之间进行关联。 在检测到故障后，根据关联将寄存器的内容存储到持久存储器位置。

公开(公告)号：WO2017188948A1

公开(公告)日：2017-11-02

申请号：PCT/US2016/029635

申请日：2016-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CAI, Qiong ,  JOHNSON, Charles ,  FARABOSCHI, Paolo

IPC: G06F9/30 ,  G06F9/38

Abstract: In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.

Abstract translation: 在一个示例中，具有动态线程映射的中央处理单元（CPU）包括一组多个核心，每个核心具有一组多个线程。 用于飞行存储器的多个线程监视器中的每一个的一组寄存器通过每个相应线程向至少第一存储器接口和第二存储器接口请求负载的数量。 第二个存储器接口比第一个存储器接口具有更大的延迟。 CPU还具有将每个线程映射和迁移到各个CPU核心的逻辑，其中仅访问至少第一和第二存储器接口中的一个的核心数量被最大化。

公开(公告)号：WO2017023252A1

公开(公告)日：2017-02-09

申请号：PCT/US2015/043165

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DAGLIS, Alexandros ,  FARABOSCHI, Paolo ,  CAI, Qiong ,  GOSTIN, Gary

IPC: G06F12/08 ,  G06F12/06

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/1441 ,  G06F12/1458 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/502

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

Abstract translation: 一种技术包括响应于与多个处理节点的给定处理节点发生的高速缓存未命中，使用用于多个处理节点的基于目录的一致性系统来调节与高速缓存未命中相关联的地址的窥探。 使用基于目录的一致性系统来调节地址是否包含在窥探域中至少部分地基于与地址相关联的多个高速缓存未命中。

公开(公告)号：WO2017091197A1

公开(公告)日：2017-06-01

申请号：PCT/US2015/062119

申请日：2015-11-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CAI, Qiong ,  FARABOSCHI, Paolo

IPC: G06F12/08

CPC classification number: G06F12/0873 ,  G06F12/0804 ,  G06F12/0848 ,  G06F2212/1024 ,  G06F2212/214

Abstract: In an example, an apparatus is described that includes a memory array. The memory array includes a volatile memory, a first non-volatile memory, and a second non-volatile memory. The memory array further includes a cache manager that controls access by a computer system to the memory array. For instance, the cache manager may carry out memory operations, including read operations, write operations, and cache evictions, in conjunction with at least one of the volatile memory, the first non-volatile memory, or the second non-volatile memory.

Abstract translation: 在一个示例中，描述了包括存储器阵列的装置。 存储器阵列包括易失性存储器，第一非易失性存储器和第二非易失性存储器。 存储器阵列进一步包括高速缓存管理器，其控制计算机系统对存储器阵列的访问。 例如，高速缓存管理器可以结合易失性存储器，第一非易失性存储器或第二非易失性存储器中的至少一个来执行包括读取操作，写入操作和高速缓存驱逐的存储器操作。 / p>

公开(公告)号：WO2018140885A1

公开(公告)日：2018-08-02

申请号：PCT/US2018/015753

申请日：2018-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： XU, Cong ,  CAI, Qiong

IPC: G06N3/08 ,  G06N3/04 ,  G06F9/22

CPC classification number: G06N3/08 ,  G06F9/4806 ,  G06N3/0454 ,  G06N3/063

Abstract: Examples disclosed herein relate to using a memory side accelerator to calculate updated deep learning parameters. A globally addressable memory includes deep learning parameters. The deep learning parameters are partitioned, where each partition is associated with a memory side accelerator. A memory side accelerator is to receive calculated gradient updates associated with its partition and calculate an update to the deep learning parameters associated with the partition.