公开(公告)号：JP2010103550A

公开(公告)日：2010-05-06

申请号：JP2009285209

申请日：2009-12-16

Applicant: Hrl Lab Llc ,  エイチアールエル ラボラトリーズ,エルエルシーHrl Laboratories, Llc

Inventor： CHOW LAP-WAI ,  BAUKUS JAMES P ,  CLARK JR WILLIAM M

IPC: H01L21/822 ,  H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/8249 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit protected against reverse engineering, and to provide a method of fabricating the same. SOLUTION: A semiconductor device includes: a field oxide layer 4 disposed on a semiconductor substrate having an opening for limiting a contact region of the semiconductor substrate; a metal plug contact 7 disposed on a portion of the field oxide located within the contact region; and a metal 10 connected to the metal plug contact, wherein the metal plug contact contacts the portion of the field oxide layer, and the portion of the field oxide layer insulates the metal plug contact from the contact region. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供防止逆向工程的集成电路，并提供其制造方法。 解决方案：半导体器件包括：设置在半导体衬底上的场氧化物层4，其具有用于限制半导体衬底的接触区域的开口; 设置在位于接触区域内的场氧化物的一部分上的金属插头触点7; 以及连接到金属插头触点的金属10，其中金属插头触点接触场氧化物层的部分，并且场氧化物层的该部分使金属插头触头与接触区域绝缘。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010118688A

公开(公告)日：2010-05-27

申请号：JP2010029399

申请日：2010-02-12

Applicant: Hrl Lab Llc ,  Raytheon Co ,  エイチアールエル ラボラトリーズ,エルエルシーHrl Laboratories, Llc ,  レイセオン カンパニーRaytheon Company

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L21/3205 ,  G06K19/073 ,  H01L21/822 ,  H01L23/52 ,  H01L23/58 ,  H01L27/04

CPC classification number: H01L27/0203 ,  G06K19/073 ,  G06K19/07363 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a technique for and structures for camouflaging an integrated circuit structure against reverse engineering. SOLUTION: The integrated circuit structure is composed of a plurality of layers of material having a controlled outline. A layer of silicide metal is disposed in active areas of the substrate and has a gap over a channel connecting adjacent active areas. The channel has a channel block structure, which appears identical under reverse engineering whether it is made conductive or insulative. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为逆向工程提供集成电路结构伪装技术和结构。 解决方案：集成电路结构由具有受控轮廓的多层材料组成。 硅化金属层设置在衬底的有源区域中，并且在连接相邻有源区的沟道之间具有间隙。 通道具有通道块结构，无论是导电还是绝缘，在逆向工程中都是相同的。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008010887A

公开(公告)日：2008-01-17

申请号：JP2007229291

申请日：2007-09-04

Applicant: Hrl Lab Llc ,  エイチアールエル ラボラトリーズ,エルエルシーHrl Laboratories, Llc

Inventor： CHOW LAP-WAI ,  BAUKUS JAMES P ,  CLARK JR WILLIAM M

IPC: H01L21/822 ,  H01L23/52 ,  H01L21/3205 ,  H01L21/8238 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit (IC) protection method cheep and easy for mounting helpful to make it impossible to actualize reverse engineering of the IC to prevent the reverse engineering of the IC specifically by making a reverse enginner very difficult to finding out the real contact of each source and drain. SOLUTION: A semiconductor device including the IC having a metal trace connected to a field oxide is provided with a reverse engineering protection. The metallization is usually connected to the gate, source, or drain of a circuit but not to an insulated field oxide, so as to make the reverse enginner make a mistake. The method is for forming the device. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供半导体集成电路（IC）保护方法，并且易于安装有助于使得不可能实现IC的逆向工程，以防止IC的逆向工程，特别是通过制造反向引导器 很难找出每个渠道和渠道的真实接触。 解决方案：包括具有连接到场氧化物的金属迹线的IC的半导体器件被提供有逆向工程保护。 金属化通常连接到电路的栅极，源极或漏极，但不连接到绝缘场氧化物，以使反向引脚发生错误。 该方法用于形成装置。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2412240A

公开(公告)日：2005-09-21

申请号：GB0512203

申请日：2005-06-15

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：WO2005124506A3

公开(公告)日：2006-05-11

申请号：PCT/US2005020093

申请日：2005-06-07

Applicant: HRL LAB LLC ,  SHU DAVID B ,  CHOW LAP-WAI ,  CLARK JR WILLIAM M

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK JR WILLIAM M

IPC: G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/00 ,  H04L9/00 ,  H04L9/06 ,  G06F9/32

CPC classification number: G06F9/30101 ,  G06F9/3001 ,  G06F9/30181 ,  G06F9/321 ,  G06F9/3836 ,  G06F21/72 ,  G06F21/75 ,  G06F21/755 ,  G06F21/85 ,  G06F2221/2123 ,  H04L9/003 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/12

Abstract: An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.

Abstract translation: 一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。 该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

公开(公告)号：GB2413436A

公开(公告)日：2005-10-26

申请号：GB0511670

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L23/58 ,  H01L27/02

Abstract: A technique for and structres for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：GB2411293A

公开(公告)日：2005-08-24

申请号：GB0510347

申请日：2003-10-16

Applicant: HRL LAB LLC ,  PROMTEK

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  YANG PAUL OU

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L29/40

Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and non functional conductive lines placed in the conductive layers. The non functional conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The non functional conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the non functional conductive lines.

公开(公告)号：GB2391986B

公开(公告)日：2005-08-10

申请号：GB0325521

申请日：2002-03-12

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  CHOW LAP-WAI ,  BAUKUS JAMES P

IPC: G11C17/18 ,  G06F12/14 ,  G11C7/12 ,  G11C7/18 ,  G11C7/24 ,  G11C16/02 ,  G11C16/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

公开(公告)号：GB2405531A

公开(公告)日：2005-03-02

申请号：GB0427115

申请日：2003-05-06

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  BAUKUS JAMES P

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.

公开(公告)号：AU2003245265A1

公开(公告)日：2003-12-02

申请号：AU2003245265

申请日：2003-05-06

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792