公开(公告)号：AU2002362394A1

公开(公告)日：2003-04-14

申请号：AU2002362394

申请日：2002-09-19

Applicant: HRL LAB LLC

Inventor： BREWER PETER D ,  POBANZ CARL W ,  MATLOUBIAN MEHRAN

IPC: G01V8/00 ,  H01L23/522 ,  H01L27/146 ,  H01L23/538

公开(公告)号：AU2794201A

公开(公告)日：2001-10-15

申请号：AU2794201

申请日：2001-01-18

Applicant: HRL LAB LLC

Inventor： POBANZ CARL W ,  MATLOUBIAN MEHRAN M

IPC: H01L29/8605 ,  G01K7/00

Abstract: A method and apparatus for substantially canceling the effects of temperature on the electrical performance of Field Effect Transistor (FET) integrated circuits (IC's) by exploiting a subtle feature of an epitaxial resistor implemented in an FET process. Specifically, the invention takes advantage of two constituent epitaxial resistor components having resistances that vary monotonically in opposite directions as functions of temperature. The invention includes a method for selecting the geometry of such an epitaxial resistor to give it either temperature invariance or a specific, useful functional temperature dependence.

公开(公告)号：WO03029772A3

公开(公告)日：2003-06-19

申请号：PCT/US0229962

申请日：2002-09-19

Applicant: HRL LAB LLC

Inventor： POBANZ CARL W ,  MATLOUBIAN MEHRAN ,  BREWER PETER D

IPC: G01V8/00 ,  H01L23/522 ,  H01L27/146 ,  H01L23/538

CPC classification number: G01V8/005 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A focal plane array for millimeter wave imaging comprising a three dimensional stack of antenna elements and radiometer microwave monolithic integrated circuits (MMICs) embedded in polymer dielectric layers built on top of a silicon substrate. Each radiometer MMIC and antenna element comprise a radiometer pixel. The silicon substrate contains integrated circuits to collect and process the signals from each radiometer pixel and generate a full-frame video signal. The array can be fabricated on a single silicon wafer or can be constructed from structures fabricated on multiple silicon wafers.

Abstract translation: 一种用于毫米波成像的焦平面阵列，包括嵌入在硅衬底顶部上的聚合物介电层中的天线元件和辐射计微波单片集成电路（MMIC）的三维堆叠。 每个辐射计MMIC和天线元件包括辐射计像素。 硅基板包含集成电路，用于收集和处理来自每个辐射计像素的信号并生成全帧视频信号。 该阵列可以制造在单个硅晶片上，或者可以由制造在多个硅晶片上的结构构成。

公开(公告)号：WO03030252B1

公开(公告)日：2004-03-18

申请号：PCT/US0229603

申请日：2002-09-18

Applicant: HRL LAB LLC

Inventor： BREWER PETER D ,  POBANZ CARL W

IPC: B81B7/00 ,  G03F7/00 ,  H01L21/768 ,  H01L21/98 ,  H01L23/522 ,  H01L25/16 ,  H01L27/06 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46

CPC classification number: B81B7/0006 ,  B81C2201/036 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76817 ,  H01L23/5222 ,  H01L23/5227 ,  H01L25/16 ,  H01L25/50 ,  H01L27/0688 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0222 ,  H05K3/005 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/1189 ,  H01L2924/00

Abstract: A method for fabricating high performance vertical and horizontal electrical connections in a three dimensional semiconductor structure. A dielectric film is imprinted with a stamp pattern at high vacuum and with precise temperature and stamping pressure control. The stamp pattern may be formed on a substrate using semiconductor fabrication techniques. After the dielectric film is stamped, residual dielectric film is removed to allow access to an underlying layer. Via and trench regions formed within the dielectric film by stamping are then metalized to provide the high performance interconnections. Multiple layers of interconnections in the three dimensional structure are provided by stacking layers of stamped and metalized dielectric films on top of each other.

Abstract translation: 在三维半导体结构中制造高性能垂直和水平电连接的方法。 电介质膜在高真空和精确的温度和冲压控制下印有图章图案。 可以使用半导体制造技术在印刷基板上形成印章图案。 在电介质膜被冲压之后，去除残留的电介质膜以允许进入下面的层。 然后通过冲压在电介质膜内形成的通孔和沟槽区被金属化以提供高性能互连。 三维结构中的多层互连通过在彼此顶部堆叠层压冲压和金属化电介质膜来提供。

公开(公告)号：WO0175982A3

公开(公告)日：2002-04-04

申请号：PCT/US0101625

申请日：2001-01-18

Applicant: HRL LAB LLC

Inventor： POBANZ CARL W ,  MATLOUBIAN MEHRAN M

IPC: H01L29/8605 ,  G01K7/00

CPC classification number: H01L29/8605

Abstract: A method and apparatus of substantially canceling the effects of temperature on the electrical performance of Field Effect Transistor (FET) integrated circuits (IC's) by exploiting a subtle feature of an epitaxial resistor implemented in an FET process. Specifically, the invention takes advantage of two constituent epitaxial resistor components having resistances that vary monotonically in opposite directions as functions of temperature. The essential components include: a plurality of ohmic contacts (100), and an isolated semi-conductor channel (102) residing in a layered semiconductor. The resistance of the epitaxial resistor R of the invention is comprised of an aggregate of resistances (FIG. 1c). The invention includes a method for selecting the geometry of such an epitaxial resistor to give it either temperature invariance or a specific, useful functional temperature dependence.

Abstract translation: 通过利用在FET工艺中实现的外延电阻的微妙特征，基本上消除了场效应晶体管（FET）集成电路（IC）的电气性能的影响的方法和装置。 具体地说，本发明利用具有作为温度函数的相反方向单调变化的电阻的两个构成的外延电阻器部件。 主要部件包括：多个欧姆接触（100）和驻留在分层半导体中的隔离半导体通道（102）。 本发明的外延电阻器R i的电阻由电阻的集合体构成（图1c）。 本发明包括一种用于选择这种外延电阻器的几何形状以提供温度不变性或特定的有用功能温度依赖性的方法。