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    Multiple program digital computer
    1.
    发明授权
    Multiple program digital computer 失效
    多个程序数字电脑

    公开(公告)号：US3676852A

    公开(公告)日：1972-07-11

    申请号：US3676852D

    申请日：1970-07-20

    Applicant: IBM

    Inventor： ABERNATHY ROGER E ,  MITROFANOFF NICHOLAS S

    IPC: G06F9/46 ,  G06F9/18

    CPC classification number: G06F9/462

    Abstract: A programmed data processor having addressable core storage, a central processing unit having one or more I/O devices connected with it, two sets of program control registers-one for each of two program levels, and a switching mechanism for operating the central processing unit in two different program levels.

    Abstract translation: 具有可寻址核心存储器的编程数据处理器，具有与其连接的一个或多个I / O设备的中央处理单元，两组程序控制寄存器 - 一个用于两个程序级别中的每一个，以及用于操作中央处理单元 在两个不同的程序级别。

    Program control for data processing machine
    4.
    发明授权
    Program control for data processing machine 失效
    数据处理机程序控制

    公开(公告)号：US3290655A

    公开(公告)日：1966-12-06

    申请号：US24793962

    申请日：1962-12-28

    Applicant: IBM

    Inventor： ABERNATHY ROGER E

    IPC: G06F9/42

    CPC classification number: G06F9/4426

    Abstract: 1,042,260. Electrical digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1963 [Dec. 28, 1962], No. 51013/63. Heading G4A. In a data processing machine in which a first register contains successive instruction addresses and a second register holds an operand address, a signal controls a switching means whereby the drive lines between the first register and the second register are interchanged. In the illustrated embodiment the drive lines of instruction address register X (Fig. 1, not shown), and A address register Y are interchanged at a branch signal in order that the next sequential instruction address in register X is not lost during the sub-routine during which A address register issues instructions. In order that the contents of A address register are not lost the drive lines of A address register and B address register are similarly interchanged. In normal working an instruction address is read into a storage address register 12 and controls the extraction of an instruction from a store 10 from which the operation is transferred to an operation code register 14 and the operand addresses to A and B address registers. The instruction address is modified by the addition of one at 24 and returned to the instruction address register X. A binary branch trigger controls the decision to branch to a sub-routine and through appropriate AND and OR circuits (Figs. 2 and 3, not shown), the drive lines to the registers are interchanged.

    Abstract translation: 1,042,260。 电子数字计算器。 国际商业机器公司 1963年12月24日[十二月 28，1962]，第51013/63号。 标题G4A。 在其中第一寄存器包含连续指令地址并且第二寄存器保存操作数地址的数据处理机中，信号控制切换装置，由此第一寄存器和第二寄存器之间的驱动线互换。 在所示实施例中，指令地址寄存器X（图1，未示出）和A地址寄存器Y的驱动线在分支信号处互换，以便寄存器X中的下一个顺序指令地址在子块 A地址寄存器发出指令的例程。 为了不丢失A地址寄存器的内容，A地址寄存器和B地址寄存器的驱动线也被相互交换。 在正常工作中，将指令地址读入存储地址寄存器12，并且控制从操作被传送到操作码寄存器14的存储器10的指令的提取以及操作数地址到A和B地址寄存器。 通过在24处添加一个指令地址并返回到指令地址寄存器X来修改指令地址。二进制分支触发器控制分支到子程序和通过适当的AND和OR电路的决定（图2和3，不是 如图所示），寄存器的驱动线互换。

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